Presentation
High-order cascade multibit /spl Sigma//spl Delta/ modulators for xDSL applications
Author/s | Río Fernández, Rocío del
![]() ![]() ![]() ![]() ![]() ![]() ![]() Medeiro Hidalgo, Fernando Pérez Verdú, Belén Rodríguez Vázquez, Ángel Benito ![]() ![]() ![]() ![]() ![]() ![]() ![]() |
Department | Universidad de Sevilla. Departamento de Electrónica y Electromagnetismo |
Publication Date | 2000 |
Deposit Date | 2019-10-24 |
Published in |
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ISBN/ISSN | 0-7803-5482-6 |
Abstract | This paper explores the use of /spl Sigma//spl Delta/ modulators for A/D conversion in xDSL applications. Two high-order multibit architectures, the 2-1-1mb modulator and a novel 2-1-1-1mb cascade (MASH), are proposed to ... This paper explores the use of /spl Sigma//spl Delta/ modulators for A/D conversion in xDSL applications. Two high-order multibit architectures, the 2-1-1mb modulator and a novel 2-1-1-1mb cascade (MASH), are proposed to achieve 14 bit dynamic range@4.4 MS/s using low oversampling ratio. They show very low sensitivity to the internal DAC linearity error, with no calibration required. Simulations show this performance can be achieved in presence of circuit imperfections, using submicron digital CMOS processes. |
Project ID. | TIC 97-0580
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Citation | Río Fernández, R.d., Medeiro Hidalgo, F., Pérez Verdú, B. y Rodríguez Vázquez, Á.B. (2000). High-order cascade multibit /spl Sigma//spl Delta/ modulators for xDSL applications. En IEEE International Symposium on Circuits and Systems (ISCAS) (II-37-II-40), Ginebra, Suiza: Institute of Electrical and Electronics Engineers. |
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HIGH-ORDER CASCADE MULTIBIT.pdf | 370.1Kb | ![]() | View/ | |