High-order cascade multibit /spl Sigma//spl Delta/ modulators for xDSL applications

Abstract

This paper explores the use of /spl Sigma//spl Delta/ modulators for A/D conversion in xDSL applications. Two high-order multibit architectures, the 2-1-1mb modulator and a novel 2-1-1-1mb cascade (MASH), are proposed to achieve 14 bit dynamic range@4.4 MS/s using low oversampling ratio. They show very low sensitivity to the internal DAC linearity error, with no calibration required. Simulations show this performance can be achieved in presence of circuit imperfections, using submicron digital CMOS processes.