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Browsing Capítulos (Tecnología Electrónica) by Author "Bellido Díaz, Manuel Jesús"
Now showing items 1-11 of 11
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Article
Application of Internode model to global power consumption estimation in SCMOS gates
Millán Calderón, Alejandro; Bellido Díaz, Manuel Jesús; Juan Chico, Jorge; Ruiz de Clavijo Vázquez, Paulino; Guerrero Martos, David; Ostúa Arangüena, Enrique; Viejo Cortés, Julián (Springer, 2005)In this paper, we present a model, Internode, that unifies the gate functional behavior and the dynamic one. It is based ...
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Chapter of Book
Computational Delay Models to Estimate the Delay of Floating Cubes in CMOS Circuits
Guerrero Martos, David; Wilke, G.; Güntzel, J.L.; Bellido Díaz, Manuel Jesús; Juan Chico, Jorge; Ruiz de Clavijo Vázquez, Paulino; Millán Calderón, Alejandro (Springer, 2003)The verification of the timing requirements of large VLSI circuits is generally performed by using simulation or timing ...
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Chapter of Book
Degradation Delay Model Extension to CMOS Gates
Juan Chico, Jorge; Bellido Díaz, Manuel Jesús; Ruiz de Clavijo Vázquez, Paulino; Acosta Jiménez, Antonio José; Valencia Barrero, Manuel (Springer, 2000)This contribution extends the Degradation Delay Model (DDM), previously developed for CMOS inverters, to simple logic ...
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Chapter of Book
Efficient and Fast Current Curve Estimation of CMOS Digital Circuits at the Logic Level
Ruiz de Clavijo Vázquez, Paulino; Juan Chico, Jorge; Bellido Díaz, Manuel Jesús; Millán Calderón, Alejandro; Guerrero Martos, David (Springer, 2002)This contribution presents a method to obtain current estimations at the logic level. This method uses a simple current ...
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Chapter of Book
Influence of Clocking Strategies on the Design of Low Switching-Noise Digital and Mixed-Signal VLSI Circuits
Acosta Jiménez, Antonio José; Jiménez, R.; Juan Chico, Jorge; Bellido Díaz, Manuel Jesús; Valencia Barrero, Manuel (Springer, 2000)This communication shows the influence of clocking schemes on the digital switching noise generation. It will be shown ...
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Chapter of Book
Logic-Level Fast Current Simulation for Digital CMOS Circuits
Ruiz de Clavijo Vázquez, Paulino; Juan Chico, Jorge; Bellido Díaz, Manuel Jesús; Millán Calderón, Alejandro; Guerrero Martos, David; Ostúa Arangüena, Enrique; Viejo Cortés, Julián (Springer, 2005)Nowadays, verification of digital integrated circuit has been focused more and more from the timing and area field to ...
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Chapter of Book
Measurement of the Switching Activity of CMOS Digital Circuits at the Gate Level
Baena Oliva, María del Carmen; Juan Chico, Jorge; Bellido Díaz, Manuel Jesús; Ruiz de Clavijo Vázquez, Paulino; Jiménez Fernández, Carlos Jesús; Valencia Barrero, Manuel (Springer, 2002)Accurate estimation of switching activity is very important in digital circuits. In this paper we present a comparison ...
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Chapter of Book
Network Time Synchronization: A Full Hardware Approach
Juan Chico, Jorge; Viejo Cortés, Julián; Bellido Díaz, Manuel Jesús (Springer, 2012)Complex digital systems are typically built on top of several abstraction levels: digital, RTL, computer, operating system ...
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Chapter of Book
Open Development Platform for Embedded Systems
Ostúa Arangüena, Enrique; Muñoz Rivera, Alejandro; Ruiz de Clavijo Vázquez, Paulino; Bellido Díaz, Manuel Jesús; Guerrero Martos, David; Millán Calderón, Alejandro (IntechOpen, 2012) -
Chapter of Book
Power Dissipation Associated to Internal Effect Transitions in Static CMOS Gates
Millán Calderón, Alejandro; Juan Chico, Jorge; Bellido Díaz, Manuel Jesús; Guerrero Martos, David; Ruiz de Clavijo Vázquez, Paulino; Viejo Cortés, Julián (Springer, 2008)Power modeling techniques have traditionally neglected the main part of the energy consumed in the internal nodes of ...
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Chapter of Book
Static Power Consumption in CMOS Gates Using Independent Bodies
Guerrero Martos, David; Millán Calderón, Alejandro; Juan Chico, Jorge; Bellido Díaz, Manuel Jesús; Ruiz de Clavijo Vázquez, Paulino; Ostúa Arangüena, Enrique; Viejo Cortés, Julián (Springer, 2007)It has been reported that the use of independent body terminals for series transistors in static bulk-CMOS gates improves ...