Ponencia
Design of a 1.2-V 130nm CMOS 13-bit@40MS/s Cascade 2-2-1 Continuous-Time ΣΔ Modulator
Autor/es | Tortosa Navas, Ramón
Aceituno Marchena, Antonio Rosa Utrera, José Manuel de la Fernández Fernández, Francisco Vidal Rodríguez Vázquez, Ángel Benito |
Departamento | Universidad de Sevilla. Departamento de Electrónica y Electromagnetismo |
Fecha de publicación | 2006 |
Fecha de depósito | 2019-08-28 |
Publicado en |
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Resumen | This paper presents the design of a continuous- time multibit cascade 2-2-1 ΣΔ modulator for broadband telecom systems. The modulator architecture has been synthesized directly in the continuous-time domain instead of using ... This paper presents the design of a continuous- time multibit cascade 2-2-1 ΣΔ modulator for broadband telecom systems. The modulator architecture has been synthesized directly in the continuous-time domain instead of using a discrete-to-continuous time transformation. This method results in a more efficient modulator in terms of noise shaping, power consumption and sensitivity to circuit element tolerances. The design of the circuit, realized in a 130nm CMOS technology, is based upon a top-down CAD methodology which combines simulation and statistical optimization at different levels of the modulator hierarchy. The estimated power consumption is 60mW from a 1.2-V supply voltage when clocked at 240MHz. Simulation results show 80-dB effective resolution within a 20-MHz signal bandwidth. |
Identificador del proyecto | TEC2004-01752/MIC |
Cita | Tortosa Navas, R., Aceituno Marchena, A., Rosa Utrera, J.M.d.l., Fernández Fernández, F.V. y Rodríguez Vázquez, Á.B. (2006). Design of a 1.2-V 130nm CMOS 13-bit@40MS/s Cascade 2-2-1 Continuous-Time ΣΔ Modulator. En Proc. of the 2006 IFIP International Conference on Very Large Scale Integration (VLSI-SoC) (267-271), Niza, Francia: Institute of Electrical and Electronics Engineers. |
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Design of a 1.2-V 130nm CMOS.pdf | 287.4Kb | [PDF] | Ver/ | |