dc.creator | Tortosa Navas, Ramón | es |
dc.creator | Aceituno Marchena, Antonio | es |
dc.creator | Rosa Utrera, José Manuel de la | es |
dc.creator | Fernández Fernández, Francisco Vidal | es |
dc.creator | Rodríguez Vázquez, Ángel Benito | es |
dc.date.accessioned | 2019-08-28T14:17:36Z | |
dc.date.available | 2019-08-28T14:17:36Z | |
dc.date.issued | 2006 | |
dc.identifier.citation | Tortosa Navas, R., Aceituno Marchena, A., Rosa Utrera, J.M.d.l., Fernández Fernández, F.V. y Rodríguez Vázquez, Á.B. (2006). Design of a 1.2-V 130nm CMOS 13-bit@40MS/s Cascade 2-2-1 Continuous-Time ΣΔ Modulator. En Proc. of the 2006 IFIP International Conference on Very Large Scale Integration (VLSI-SoC) (267-271), Niza, Francia: Institute of Electrical and Electronics Engineers. | |
dc.identifier.uri | https://hdl.handle.net/11441/88767 | |
dc.description.abstract | This paper presents the design of a continuous- time multibit cascade 2-2-1 ΣΔ modulator for broadband telecom systems. The modulator architecture has been synthesized directly in the continuous-time domain instead of using a discrete-to-continuous time transformation. This method results in a more efficient modulator in terms of noise shaping, power consumption and sensitivity to circuit element tolerances. The design of the circuit, realized in a 130nm CMOS technology, is based upon a top-down CAD methodology which combines simulation and statistical optimization at different levels of the modulator hierarchy. The estimated power consumption is 60mW from a 1.2-V supply voltage when clocked at 240MHz. Simulation results show 80-dB effective resolution within a 20-MHz signal bandwidth. | es |
dc.description.sponsorship | Ministerio de Educación y Ciencia TEC2004-01752/MIC | es |
dc.format | application/pdf | es |
dc.language.iso | eng | es |
dc.publisher | Institute of Electrical and Electronics Engineers | es |
dc.relation.ispartof | Proc. of the 2006 IFIP International Conference on Very Large Scale Integration (VLSI-SoC) (2006), p 267-271 | |
dc.rights | Attribution-NonCommercial-NoDerivatives 4.0 Internacional | * |
dc.rights.uri | http://creativecommons.org/licenses/by-nc-nd/4.0/ | * |
dc.subject | Continuous-Time Circuits | es |
dc.subject | Sigma-Delta Modulators | es |
dc.subject | Low-Voltage | es |
dc.title | Design of a 1.2-V 130nm CMOS 13-bit@40MS/s Cascade 2-2-1 Continuous-Time ΣΔ Modulator | es |
dc.type | info:eu-repo/semantics/conferenceObject | es |
dcterms.identifier | https://ror.org/03yxnpp24 | |
dc.type.version | info:eu-repo/semantics/acceptedVersion | es |
dc.rights.accessRights | info:eu-repo/semantics/openAccess | es |
dc.contributor.affiliation | Universidad de Sevilla. Departamento de Electrónica y Electromagnetismo | es |
dc.relation.projectID | TEC2004-01752/MIC | es |
idus.format.extent | 5 p. | es |
dc.publication.initialPage | 267 | es |
dc.publication.endPage | 271 | es |
dc.eventtitle | Proc. of the 2006 IFIP International Conference on Very Large Scale Integration (VLSI-SoC) | es |
dc.eventinstitution | Niza, Francia | es |