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Gate-Level Simulation of CMOS Circuits Using the IDDM Model

 

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Opened Access Gate-Level Simulation of CMOS Circuits Using the IDDM Model
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Author: Bellido Díaz, Manuel Jesús
Juan Chico, Jorge
Ruiz de Clavijo Vázquez, Paulino
Acosta Jiménez, Antonio José
Valencia Barrero, Manuel
Department: Universidad de Sevilla. Departamento de Tecnología Electrónica
Universidad de Sevilla. Departamento de Electrónica y Electromagnetismo
Date: 2001
Published in: ISCAS 2001. The 2001 IEEE International Symposium on Circuits and Systems (2001), p 483-486
ISBN/ISSN: 0-7803-6685-9
Document type: Presentation
Abstract: Timing verification of digital CMOS circuits is a key point in the design process. In this contribution we present the extension to gates of the Inertial and Degradation Delay Model for logic timing simulation which is able to take account of the propagation of arbitrarily narrow pulses. As a result, the model is ready to be applied to the simulation and verification of complex circuits. Simulation results show an accuracy similar to HSPICE and greatly improved precision over conventional delay models.
Cite: Bellido Díaz, M.J., Juan Chico, J., Ruiz de Clavijo Vázquez, P., Acosta Jiménez, A.J. y Valencia Barrero, M. (2001). Gate-Level Simulation of CMOS Circuits Using the IDDM Model. En ISCAS 2001. The 2001 IEEE International Symposium on Circuits and Systems (483-486), Sidney, Australia: IEEE Computer Society.
Size: 382.9Kb
Format: PDF

URI: http://hdl.handle.net/11441/52452

DOI: 10.1109/ISCAS.2001.922090

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