Presentation
A 0.5 /spl mu/m CMOS CNN analog random access memory chip for massive image processing
Author/s | Carmona Galán, Ricardo
Espejo Meana, Servando Carlos Domínguez Castro, Rafael Rodríguez Vázquez, Ángel Benito Roska, Tamás Kozek, Tibor Chua, Leon O. |
Department | Universidad de Sevilla. Departamento de Electrónica y Electromagnetismo |
Publication Date | 1998 |
Deposit Date | 2020-02-25 |
Published in |
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ISBN/ISSN | 0-7803-4867-2 |
Abstract | An analog RAM has been designed to act as a cache memory for a CNN Universal Machine. Hence, all the non-standard chips are available for the CNN Chipset architecture. Time-multiplexed analog routines in the CNN processor ... An analog RAM has been designed to act as a cache memory for a CNN Universal Machine. Hence, all the non-standard chips are available for the CNN Chipset architecture. Time-multiplexed analog routines in the CNN processor require fast and efficient short-time signal storage in an analog buffer. This can be achieved by an extended sample and hold scheme able to address every sample to specific memory locations. Several arrays of capacitors are multiplexed sharing controlling circuitry and I/O buses. The design has the following key parameters: 637 analog memory cells/mm/sup 2/ with 0.4% accuracy, 100 ns access time and 170 ms storage time (within 1% error). |
Project ID. | FDF49620-97-1-0220-03/98
N00014-98-1- 0052 |
Citation | Carmona Galán, R., Espejo Meana, S.C., Domínguez Castro, R., Rodríguez Vázquez, Á.B., Roska, T., Kozek, T. y Chua, L.O. (1998). A 0.5 /spl mu/m CMOS CNN analog random access memory chip for massive image processing. En 5th IEEE International Workshop on Cellular Neural Networks and Their Applications (271-276), Londres, Reino Unido: Institute of Electrical and Electronics Engineers. |
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A 0.5pm CMOS CNN Analog Random.pdf | 750.9Kb | [PDF] | View/ | |