Ponencia
Spiking row-by-row FPGA Multi-kernel and Multi-layer Convolution Processor.
Autor/es | Tapiador Morales, Ricardo
Ríos Navarro, José Antonio Domínguez Morales, Juan Pedro Gutiérrez Galán, Daniel Linares Barranco, Alejandro |
Departamento | Universidad de Sevilla. Departamento de Arquitectura y Tecnología de Computadores |
Fecha de publicación | 2019 |
Fecha de depósito | 2020-02-05 |
Publicado en |
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ISBN/ISSN | 978-1-7281-4884-7 1946-1488 |
Resumen | Spiking convolutional neural networks have become
a novel approach for machine vision tasks, due to the latency
to process an input stimulus from a scene, and the low power
consumption of these kind of solutions. ... Spiking convolutional neural networks have become a novel approach for machine vision tasks, due to the latency to process an input stimulus from a scene, and the low power consumption of these kind of solutions. Event-based systems only perform sum operations instead of sum of products of framebased systems. In this work an upgrade of a neuromorphic event-based convolution accelerator for SCNN, which is able to perform multiple layers with different kernel sizes, is presented. The system has a latency per layer from 1.44 μs to 9.98μs for kernel sizes from 1x1 to 7x7. |
Cita | Tapiador Morales, R., Ríos Navarro, J.A., Domínguez Morales, J.P., Gutiérrez Galán, D. y Linares Barranco, A. (2019). Spiking row-by-row FPGA Multi-kernel and Multi-layer Convolution Processor.. En FPL 2019: 29th International Conference on Field Programmable Logic and Applications (248-249), Barcelona, España: IEEE Computer Society. |
Ficheros | Tamaño | Formato | Ver | Descripción |
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Spiking Row-by-Row FPGA.pdf | 242.1Kb | [PDF] | Ver/ | |