dc.creator | Tapiador Morales, Ricardo | es |
dc.creator | Ríos Navarro, José Antonio | es |
dc.creator | Domínguez Morales, Juan Pedro | es |
dc.creator | Gutiérrez Galán, Daniel | es |
dc.creator | Linares Barranco, Alejandro | es |
dc.date.accessioned | 2020-02-05T11:22:24Z | |
dc.date.available | 2020-02-05T11:22:24Z | |
dc.date.issued | 2019 | |
dc.identifier.citation | Tapiador Morales, R., Ríos Navarro, J.A., Domínguez Morales, J.P., Gutiérrez Galán, D. y Linares Barranco, A. (2019). Spiking row-by-row FPGA Multi-kernel and Multi-layer Convolution Processor.. En FPL 2019: 29th International Conference on Field Programmable Logic and Applications (248-249), Barcelona, España: IEEE Computer Society. | |
dc.identifier.isbn | 978-1-7281-4884-7 | es |
dc.identifier.issn | 1946-1488 | es |
dc.identifier.uri | https://hdl.handle.net/11441/92761 | |
dc.description.abstract | Spiking convolutional neural networks have become
a novel approach for machine vision tasks, due to the latency
to process an input stimulus from a scene, and the low power
consumption of these kind of solutions. Event-based systems only
perform sum operations instead of sum of products of framebased
systems. In this work an upgrade of a neuromorphic
event-based convolution accelerator for SCNN, which is able to
perform multiple layers with different kernel sizes, is presented.
The system has a latency per layer from 1.44 μs to 9.98μs for
kernel sizes from 1x1 to 7x7. | es |
dc.format | application/pdf | es |
dc.language.iso | eng | es |
dc.publisher | IEEE Computer Society | es |
dc.relation.ispartof | FPL 2019: 29th International Conference on Field Programmable Logic and Applications (2019), p 248-249 | |
dc.rights | Attribution-NonCommercial-NoDerivatives 4.0 Internacional | * |
dc.rights.uri | http://creativecommons.org/licenses/by-nc-nd/4.0/ | * |
dc.subject | Spiking Convolutional Neural Networks | es |
dc.subject | FPGA | es |
dc.subject | Computer vision | es |
dc.subject | Neuromorphic engineering | es |
dc.title | Spiking row-by-row FPGA Multi-kernel and Multi-layer Convolution Processor. | es |
dc.type | info:eu-repo/semantics/conferenceObject | es |
dcterms.identifier | https://ror.org/03yxnpp24 | |
dc.type.version | info:eu-repo/semantics/submittedVersion | es |
dc.rights.accessRights | info:eu-repo/semantics/openAccess | es |
dc.contributor.affiliation | Universidad de Sevilla. Departamento de Arquitectura y Tecnología de Computadores | es |
dc.relation.publisherversion | https://ieeexplore.ieee.org/document/8892011 | es |
dc.identifier.doi | 10.1109/FPL.2019.00046 | es |
dc.contributor.group | Universidad de Sevilla. TEP-108: Robótica y Tecnología de Computadores Aplicada a la Rehabilitación | es |
idus.format.extent | 2 | es |
dc.publication.initialPage | 248 | es |
dc.publication.endPage | 249 | es |
dc.eventtitle | FPL 2019: 29th International Conference on Field Programmable Logic and Applications | es |
dc.eventinstitution | Barcelona, España | es |
dc.relation.publicationplace | New York, USA | es |