Ponencia
Live Demonstration: Neuromorphic Row-by-Row Multi-convolution FPGA Processor-SpiNNaker architecture for Dynamic-Vision Feature Extraction
Autor/es | Tapiador Morales, Ricardo
Domínguez Morales, Juan Pedro Gutiérrez Galán, Daniel Ríos Navarro, José Antonio Jiménez Fernández, Ángel Francisco Linares Barranco, Alejandro |
Departamento | Universidad de Sevilla. Departamento de Arquitectura y Tecnología de Computadores |
Fecha de publicación | 2019 |
Fecha de depósito | 2020-01-23 |
Publicado en |
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ISBN/ISSN | 978-1-7281-0397-6 2158-1525 |
Resumen | In this demonstration a spiking neural network
architecture for vision recognition using an FPGA spiking
convolution processor, based on leaky integrate and fire neurons
(LIF) and a SpiNNaker board is presented. The ... In this demonstration a spiking neural network architecture for vision recognition using an FPGA spiking convolution processor, based on leaky integrate and fire neurons (LIF) and a SpiNNaker board is presented. The network has been trained with Poker-DVS dataset in order to classify the four different card symbols. The spiking convolution processor extracts features from images in form of spikes, computes by one layer of 64 convolutions. These features are sent to an OKAERtool board that converts from AER to 2-7 protocol to be classified by a spiking neural network deployed on a SpiNNaker platform. |
Cita | Tapiador Morales, R., Domínguez Morales, J.P., Gutiérrez Galán, D., Rios Navarro, A., Jiménez Fernández, Á.F. y Linares Barranco, A. (2019). Live Demonstration: Neuromorphic Row-by-Row Multi-convolution FPGA Processor-SpiNNaker architecture for Dynamic-Vision Feature Extraction. En ISCAS 2019: IEEE International Symposium on Circuits and Systems Sapporo, Japan: IEEE Computer Society. |
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