dc.creator | Tapiador Morales, Ricardo | es |
dc.creator | Domínguez Morales, Juan Pedro | es |
dc.creator | Gutiérrez Galán, Daniel | es |
dc.creator | Ríos Navarro, José Antonio | es |
dc.creator | Jiménez Fernández, Ángel Francisco | es |
dc.creator | Linares Barranco, Alejandro | es |
dc.date.accessioned | 2020-01-23T10:56:10Z | |
dc.date.available | 2020-01-23T10:56:10Z | |
dc.date.issued | 2019 | |
dc.identifier.citation | Tapiador Morales, R., Domínguez Morales, J.P., Gutiérrez Galán, D., Rios Navarro, A., Jiménez Fernández, Á.F. y Linares Barranco, A. (2019). Live Demonstration: Neuromorphic Row-by-Row Multi-convolution FPGA Processor-SpiNNaker architecture for Dynamic-Vision Feature Extraction. En ISCAS 2019: IEEE International Symposium on Circuits and Systems Sapporo, Japan: IEEE Computer Society. | |
dc.identifier.isbn | 978-1-7281-0397-6 | es |
dc.identifier.issn | 2158-1525 | es |
dc.identifier.uri | https://hdl.handle.net/11441/92197 | |
dc.description.abstract | In this demonstration a spiking neural network
architecture for vision recognition using an FPGA spiking
convolution processor, based on leaky integrate and fire neurons
(LIF) and a SpiNNaker board is presented. The network has
been trained with Poker-DVS dataset in order to classify the
four different card symbols. The spiking convolution processor
extracts features from images in form of spikes, computes by
one layer of 64 convolutions. These features are sent to an
OKAERtool board that converts from AER to 2-7 protocol
to be classified by a spiking neural network deployed on a
SpiNNaker platform. | es |
dc.format | application/pdf | es |
dc.language.iso | eng | es |
dc.publisher | IEEE Computer Society | es |
dc.relation.ispartof | ISCAS 2019: IEEE International Symposium on Circuits and Systems (2019), | |
dc.rights | Attribution-NonCommercial-NoDerivatives 4.0 Internacional | * |
dc.rights.uri | http://creativecommons.org/licenses/by-nc-nd/4.0/ | * |
dc.subject | Address-event-representation | es |
dc.subject | Spiking neural network | es |
dc.subject | FPGA | es |
dc.subject | Neuromorphic engineering | es |
dc.subject | SpiNNaker | es |
dc.title | Live Demonstration: Neuromorphic Row-by-Row Multi-convolution FPGA Processor-SpiNNaker architecture for Dynamic-Vision Feature Extraction | es |
dc.type | info:eu-repo/semantics/conferenceObject | es |
dcterms.identifier | https://ror.org/03yxnpp24 | |
dc.type.version | info:eu-repo/semantics/submittedVersion | es |
dc.rights.accessRights | info:eu-repo/semantics/openAccess | es |
dc.contributor.affiliation | Universidad de Sevilla. Departamento de Arquitectura y Tecnología de Computadores | es |
dc.relation.publisherversion | https://ieeexplore.ieee.org/document/8702233 | es |
dc.identifier.doi | 10.1109/ISCAS.2019.8702233 | es |
dc.contributor.group | Universidad de Sevilla. TEP-108: Robótica y Tecnología de Computadores Aplicada a la Rehabilitación | es |
idus.format.extent | 1 | es |
dc.eventtitle | ISCAS 2019: IEEE International Symposium on Circuits and Systems | es |
dc.eventinstitution | Sapporo, Japan | es |
dc.relation.publicationplace | New York, USA | es |