Capítulo de Libro
Network Time Synchronization: A Full Hardware Approach
Autor/es | Juan Chico, Jorge
Viejo Cortés, Julián Bellido Díaz, Manuel Jesús |
Departamento | Universidad de Sevilla. Departamento de Tecnología Electrónica |
Fecha de publicación | 2012 |
Fecha de depósito | 2017-01-25 |
Publicado en |
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ISBN/ISSN | 978-3-642-36156-2 0302-9743 |
Resumen | Complex digital systems are typically built on top of several
abstraction levels: digital, RTL, computer, operating system and
software application. Each abstraction level greatly facilitates the design
task at the cost ... Complex digital systems are typically built on top of several abstraction levels: digital, RTL, computer, operating system and software application. Each abstraction level greatly facilitates the design task at the cost of paying in performance and hardware resources usage. Network time synchronization is a good example of a complex system using several abstraction levels since the traditional solutions are a software application running on top of several software and hardware layers. In this contribution we study the case where a standards-compliant network time synchronization solution is fully implemented in hardware on a FPGA chip doing without any software layer. This solution makes it possible to implement very compact, inexpensive and accurate synchronization systems to be used either stand-alone or as embedded cores. Some general aspects of the design experience are commented together with some figures of merit. As a conclusion, full hardware implementations of complex digital systems should be seen as a feasible design option, from which great performance advantages can be expected, provided that we can find a suitable set of tools and control the design development costs. |
Agencias financiadoras | Ministerio de Ciencia e Innovación (MICIN). España |
Identificador del proyecto | HIPERSYS TEC2011-27936 |
Cita | Juan Chico, J., Viejo Cortés, J., y Bellido Díaz, M.J. (2012). Network Time Synchronization: A Full Hardware Approach. En Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation. PATMOS 2012. Lecture Notes in Computer Science, vol 7606 (pp. 225-234). Berlin: Springer. |
Ficheros | Tamaño | Formato | Ver | Descripción |
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Network time.pdf | 303.6Kb | [PDF] | Ver/ | |