dc.creator | Juan Chico, Jorge | es |
dc.creator | Viejo Cortés, Julián | es |
dc.creator | Bellido Díaz, Manuel Jesús | es |
dc.date.accessioned | 2017-01-25T08:55:16Z | |
dc.date.available | 2017-01-25T08:55:16Z | |
dc.date.issued | 2012 | |
dc.identifier.citation | Juan Chico, J., Viejo Cortés, J., y Bellido Díaz, M.J. (2012). Network Time Synchronization: A Full Hardware Approach. En Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation. PATMOS 2012. Lecture Notes in Computer Science, vol 7606 (pp. 225-234). Berlin: Springer. | |
dc.identifier.isbn | 978-3-642-36156-2 | es |
dc.identifier.issn | 0302-9743 | es |
dc.identifier.uri | http://hdl.handle.net/11441/52737 | |
dc.description.abstract | Complex digital systems are typically built on top of several
abstraction levels: digital, RTL, computer, operating system and
software application. Each abstraction level greatly facilitates the design
task at the cost of paying in performance and hardware resources usage.
Network time synchronization is a good example of a complex system
using several abstraction levels since the traditional solutions are a software
application running on top of several software and hardware layers.
In this contribution we study the case where a standards-compliant network
time synchronization solution is fully implemented in hardware on
a FPGA chip doing without any software layer. This solution makes it
possible to implement very compact, inexpensive and accurate synchronization
systems to be used either stand-alone or as embedded cores.
Some general aspects of the design experience are commented together
with some figures of merit. As a conclusion, full hardware implementations
of complex digital systems should be seen as a feasible design
option, from which great performance advantages can be expected, provided
that we can find a suitable set of tools and control the design
development costs. | es |
dc.format | application/pdf | es |
dc.language.iso | eng | es |
dc.publisher | Springer | es |
dc.relation.ispartof | Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation. PATMOS 2012. Lecture Notes in Computer Science, vol 7606 | es |
dc.rights | Attribution-NonCommercial-NoDerivatives 4.0 Internacional | * |
dc.rights.uri | http://creativecommons.org/licenses/by-nc-nd/4.0/ | * |
dc.subject | digital systems | es |
dc.subject | hardware | es |
dc.subject | network time synchronization | es |
dc.subject | FPGA | es |
dc.title | Network Time Synchronization: A Full Hardware Approach | es |
dc.type | info:eu-repo/semantics/bookPart | es |
dcterms.identifier | https://ror.org/03yxnpp24 | |
dc.type.version | info:eu-repo/semantics/acceptedVersion | es |
dc.rights.accessRights | info:eu-repo/semantics/openAccess | es |
dc.contributor.affiliation | Universidad de Sevilla. Departamento de Tecnología Electrónica | es |
dc.relation.projectID | HIPERSYS TEC2011-27936 | es |
dc.relation.publisherversion | http://link.springer.com/chapter/10.1007%2F978-3-642-36157-9_23 | es |
dc.contributor.sponsorship | Ministerio de Ciencia e Innovación HIPERSYS TEC2011-27936 | |
dc.identifier.doi | 10.1007/978-3-642-36157-9_23 | es |
dc.contributor.group | Universidad de Sevilla. TIC204: Investigación y Desarrollo Digital (ID2) | es |
idus.format.extent | 10 | es |
dc.publication.initialPage | 225 | es |
dc.publication.endPage | 234 | es |
dc.relation.publicationplace | Berlin | es |
dc.contributor.funder | Ministerio de Ciencia e Innovación (MICIN). España | |