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Ponencia
Algorithms to get the maximum operation frequency for skew-tolerant clocking schemes
(Society of Photo-Optical Instrumentation Engineers (SPIE), 2005)
Nowadays it is not possible to neglect the delay of interconnection lines. The die size is rising very fast, and the delay of the interconnection lines grows quadrically with it. Also, the fact that the gate delay keeps ...
Ponencia
Gestión Global de Clientes para Establecimientos Hoteleros
(Asociación para el Desarrollo de la Ingeniería de Organización (ADINGOR), 2006)
Analizando la situación que se vive actualmente, se llegó a la conclusión de que en e panorama actual, el sector de la hostelería presenta limitaciones importantes respecto a la posibilidad de aumentar la cuota de mercado ...
Ponencia
HALOTIS: high accuracy LOgic TIming simulator with inertial and degradation delay model
(IEEE Computer Society, 2001)
This communication presents HALOTIS, a novel high accuracy logic timing simulation tool, that incorporates a new simulation algorithm based on different concepts for transitions and events. This new simulation algorithm ...
Ponencia
Term weighting: novel fuzzy logic based method vs. classical tf-idf method for web information extraction
(Institute for Systems and Technologies of Information, Control and Communication (Insticc), 2009)
Solving Term Weighting problem is one of the most important tasks for Information Retrieval and Information Extraction. Tipically, the TF-IDF method have been widely used for determining the weight of a term. In this ...
Ponencia
Modelos de adaptación de los programas formativos al espacio europeo
(Universidad Politécnica de Valencia, 2004)
Ante el volumen de información a veces contradictoria acerca de la educación, en este artículo pretendemos presentar una propuesta de modelo de formación para ayudar en la medida de lo posible a la creación de programas ...
Ponencia
Automatic logic synthesis for parallel alternating latches clocking schemes
(SPIE Digital Library, 2007)
This paper proposes a VHDL coding technique that allows for the automatic synthesis of digital circuits using the so called Parallel Alternating Latches Clocking Schemes (PALACS). The proposed method greatly improves ...
Ponencia
A CMOS Bio-Impedance Measurement System
(IEEE Computer Society, 2009)
This paper proposes a new method for bio-impedance measurement useful to 2D processing of cell cultures. It allows to represent biological samples by using a new impedance sensing method, and exploiting the electrode-to-cell ...
Ponencia
Information Systems for Improving Competition in Deregulated Electricity Market
(Escola Superior de Tecnologia de Setúba, 2000)
Capítulo de Libro
Logic-Level Fast Current Simulation for Digital CMOS Circuits
(Springer, 2005)
Nowadays, verification of digital integrated circuit has been focused more and more from the timing and area field to current and power estimations. The main problem with this kind of verification is on the lack of ...
Ponencia
Sistema integrado de simulación y evaluación docente de la automatización de procesos industriales
(Gráficas de Vigo, 2001)
Ante la necesidad de proporcionar a los alumnos de prácticas de Automatización una herramienta que les permita comprobar el resultado de sus ejercicios, se genera una aplicación para entorno windows capaz de simular las ...