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Ponencia
ADKI: un sistema web de adquisición de datos bajo Linux
(Universidad Politécnica de Valencia, 2004)
Esta contribución presenta una aplicación genérica de adquisición de datos y control para sistemas simples que incorpora el registro histórico de la actividad del sistema y la capacidad de consulta y gestión de la ...
Capítulo de Libro
Power Dissipation Associated to Internal Effect Transitions in Static CMOS Gates
(Springer, 2008)
Power modeling techniques have traditionally neglected the main part of the energy consumed in the internal nodes of static CMOS gates: the power dissipated by input transitions that do not produce output switching. In ...
Ponencia
Design of a FFT/IFFT module as an IP core suitable for embedded systems
(IEEE Computer Society, 2007)
In this work, we have laid the foundations that allow us to accomplish the implementation of a FFT/IFFT module as an IP core. The main objective is to design a configurable optimized core that can be integrated as a ...
Capítulo de Libro
Measurement of the Switching Activity of CMOS Digital Circuits at the Gate Level
(Springer, 2002)
Accurate estimation of switching activity is very important in digital circuits. In this paper we present a comparison between the evaluation of the switching activity calculated using logic (Verilog) and electrical (HSPICE) ...
Ponencia
Delay and power consumption of static bulk-CMOS gates using independent bodies
(IEEE Computer Society, 2009)
Digital designs implemented using SOI processes employ separated bodies for each transistor. This approach is not usually considered in digital bulk-CMOS design because of its obvious area penalty. However, the advantages ...
Capítulo de Libro
Static Power Consumption in CMOS Gates Using Independent Bodies
(Springer, 2007)
It has been reported that the use of independent body terminals for series transistors in static bulk-CMOS gates improves their timing and dynamic power characteristics. In this paper, the static power consumption of ...
Ponencia
Diseño e Implementación Óptima de Periféricos de DSP con System Generator para Microblaze
(IBERCHIP, 2006)
Con este trabajo pretendemos analizar como se lleva a cabo el diseño de periféricos de DSP utilizando uno de los nuevos entornos de diseño de alto nivel: System Generator for DSP. Así, en este documento el objetivo es ...
Ponencia
Algorithms to get the maximum operation frequency for skew-tolerant clocking schemes
(Society of Photo-Optical Instrumentation Engineers (SPIE), 2005)
Nowadays it is not possible to neglect the delay of interconnection lines. The die size is rising very fast, and the delay of the interconnection lines grows quadrically with it. Also, the fact that the gate delay keeps ...
Ponencia
HALOTIS: high accuracy LOgic TIming simulator with inertial and degradation delay model
(IEEE Computer Society, 2001)
This communication presents HALOTIS, a novel high accuracy logic timing simulation tool, that incorporates a new simulation algorithm based on different concepts for transitions and events. This new simulation algorithm ...
Ponencia
Automatic logic synthesis for parallel alternating latches clocking schemes
(SPIE Digital Library, 2007)
This paper proposes a VHDL coding technique that allows for the automatic synthesis of digital circuits using the so called Parallel Alternating Latches Clocking Schemes (PALACS). The proposed method greatly improves ...