Listar Instituto de Microelectrónica de Sevilla (IMSE-CNM) por autor "Delgado Restituto, Manuel"
Mostrando ítems 21-40 de 56
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Ponencia
An auto-calibrated neural spike recording channel with feature extraction capabilities
(The International Society for Optics and Photonics, 2011)This paper presents a power efficient architecture for a neural spike recording channel. The channel offers a selfcalibration ...
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Ponencia
An Embedded 12-bit 80MS/s A/D/A Interface for Power-Line Communications in 0.13μm Pure Digital CMOS Technology
(Institute of Electrical and Electronics Engineers, 2005)This paper presents an embedded interface, comprising both A/D and D/A converters, which has been implemented in a 0.13μm ...
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Artículo
An ultralow-power mixed-signal back end for passive sensor UHF RFID transponders
(Institute of Electrical and Electronics Engineers, 2012)This paper describes the design of mixed-signal back end for an ultrahigh-frequency sensor-enabled radio-frequency ...
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Ponencia
Artifact-Aware Analogue/Mixed-Signal Front-Ends for Neural Recording Applications
(Institute of Electrical and Electronics Engineers, 2019)This paper presents a brief review of techniques to overcome the problems associated with artifacts in analog frontends ...
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Artículo
CMOS 2.4μm chaotic oscillator: Experimental verification of chaotic encryption of audio
(Institution of Engineering and Technology, 1996)The Letter reports the first experimental verification of chaotic encryption of audio using custom monolithic chaotic ...
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Ponencia
CMOS current-mode chaotic neurons
(Institute of Electrical and Electronics Engineers, 1994)This paper presents two nonlinear CMOS current-mode circuits that implement neuron soma equations for chaotic neural ...
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Ponencia
CMOS design of chaotic oscillators using state variables: a monolithic Chua's circuit
(Institute of Electrical and Electronics Engineers, 1993)This paper presents design considerations for monolithic implementation of piecewise-linear (PWL) dynamic systems in CMOS ...
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Ponencia
Current-mode building blocks for CMOS-VLSI design of chaotic neural networks
(Institute of Electrical and Electronics Engineers, 1994)This paper presents two nonlinear CMOS current-mode circuits that implement neuron soma equations for chaotic neural ...
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Ponencia
Current-mode piecewise-linear function generators
(Institute of Electrical and Electronics Engineers, 1996)We present a systematic design technique for current-mode piecewise-linear (PWL) function generators. It uses two building ...
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Artículo
Design considerations for integrated continuous-time chaotic oscillators
(Institute of Electrical and Electronics Engineers, 1998)This paper presents an optimization procedure to choose the chaotic state equation which is best suited for implementation ...
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Ponencia
Discrete-time integrated circuits for chaotic communication
(Institute of Electrical and Electronics Engineers, 1997)This paper gives design considerations for the synthesis of analog discrete-time encoder-decoder pairs based on digital ...
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Ponencia
Electrical-level synthesis of pipeline ADCs
(Institute of Electrical and Electronics Engineers, 2008)This paper presents a design tool for the synthesis of pipeline ADCs which is able to optimally map high-level converter ...
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Artículo
Enhanced Sensitivity of CMOS Image Sensors by Stacked Diodes
(Institute of Electrical and Electronics Engineers, 2016)We have investigated and compared the performance of photodiodes built with stacked p/n junctions operating in parallel ...
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Ponencia
Experimental verification of chaotic encryption of audio using monolithic chaotic modulators
(SPIE- The International Society for Optical Engineering, 1995)This paper reports the first experimental verification of chaotic encryption of audio signals using integrated circuits. ...
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Ponencia
Generation of technology-portable flexible analog blocks
(Institute of Electrical and Electronics Engineers, 2002)This paper introduces a complete methodology for retargeting of analog blocks to different sets of specifications, even ...
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Artículo
Highly Linear 2,5-V CMOS ΣΔ Modulator for ADSL+
(Institute of Electrical and Electronics Engineers, 2004)We present a 90-dB spurious-free dynamic range sigma–delta modulator (ΣΔM) for asymmetric digital subscriber line applications ...
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Ponencia
IC design for spread spectrum communication exploiting chaos
(Institute of Electrical and Electronics Engineers, 1996)This paper presents a 2.4 /spl mu/m CMOS IC prototype which includes a programmable chaotic generator and some interface ...
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Ponencia
In vivo measurements with a 64-channel extracellular neural recording integrated circuit
(Institute of Electrical and Electronics Engineers, 2014)This paper presents in vivo measurements obtained from an implantable 64-channel neural recording Application Specific ...
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Ponencia
Integer-based digital processor for the estimation of phase synchronization between neural signals
(Institute of Electrical and Electronics Engineers, 2016)This paper reports a low area, low power, integer-based neural digital processor for the calculation of phase synchronization ...
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Artículo
Integrated chaos generators
(Institute of Electrical and Electronics Engineers, 2002)This paper surveys the different design issues, from mathematical model to silicon, involved on the design of integrated circuits for the generation of chaotic behavior.