Presentation
Fully Digital AER Convolution Chip for Vision Processing
Author/s | Camuñas Mesa, Luis Alejandro
Acosta Jiménez, Antonio José Serrano Gotarredona, María Teresa Linares Barranco, Bernabé |
Department | Universidad de Sevilla. Departamento de Arquitectura y Tecnología de Computadores Universidad de Sevilla. Departamento de Electrónica y Electromagnetismo |
Publication Date | 2008 |
Deposit Date | 2020-10-22 |
Published in |
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ISBN/ISSN | 978-1-4244-1683-7 0271-4302 |
Abstract | We present a neuromorphic fully digital convolution
microchip for Address Event Representation (AER)
spike-based processing systems. This microchip computes
2-D convolutions with a programmable kernel in
real time. It ... We present a neuromorphic fully digital convolution microchip for Address Event Representation (AER) spike-based processing systems. This microchip computes 2-D convolutions with a programmable kernel in real time. It operates on a pixel array of size 32 x 32, and the kernel is programmable and can be of arbitrary shape and size up to 32 x 32 pixels. The chip receives and generates data in AER format, which is asynchronous and digital. The paper describes the architecture of the chip, the test setup, and experimental results obtained from a fabricated prototype. |
Funding agencies | European Union (UE) Comisión Interministerial de Ciencia y Tecnología (CICYT). España Ministerio de Educación y Ciencia (MEC). España Junta de Andalucía |
Project ID. | IST-2001-34124 (CAVIAR)
TIC-2003-08164-C03-01 TEC2006-11730-C03-01 P06-TIC-01417 |
Citation | Camuñas Mesa, L.A., Acosta Jiménez, A.J., Serrano Gotarredona, M.T. y Linares Barranco, B. (2008). Fully Digital AER Convolution Chip for Vision Processing. En ISCAS 2008: IEEE International Symposium on Circuits and Systems (652-655), Seattle, USA: IEEE Computer Society. |
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