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Fully Digital AER Convolution Chip for Vision Processing

dc.creatorCamuñas Mesa, Luis Alejandroes
dc.creatorAcosta Jiménez, Antonio Josées
dc.creatorSerrano Gotarredona, María Teresaes
dc.creatorLinares Barranco, Bernabées
dc.date.accessioned2020-10-22T07:18:29Z
dc.date.available2020-10-22T07:18:29Z
dc.date.issued2008
dc.identifier.citationCamuñas Mesa, L.A., Acosta Jiménez, A.J., Serrano Gotarredona, M.T. y Linares Barranco, B. (2008). Fully Digital AER Convolution Chip for Vision Processing. En ISCAS 2008: IEEE International Symposium on Circuits and Systems (652-655), Seattle, USA: IEEE Computer Society.
dc.identifier.isbn978-1-4244-1683-7es
dc.identifier.issn0271-4302es
dc.identifier.urihttps://hdl.handle.net/11441/102133
dc.description.abstractWe present a neuromorphic fully digital convolution microchip for Address Event Representation (AER) spike-based processing systems. This microchip computes 2-D convolutions with a programmable kernel in real time. It operates on a pixel array of size 32 x 32, and the kernel is programmable and can be of arbitrary shape and size up to 32 x 32 pixels. The chip receives and generates data in AER format, which is asynchronous and digital. The paper describes the architecture of the chip, the test setup, and experimental results obtained from a fabricated prototype.es
dc.description.sponsorshipEuropean Union IST-2001-34124 (CAVIAR)es
dc.description.sponsorshipComisión Interministerial de Ciencia y Tecnología TIC-2003-08164-C03-01es
dc.description.sponsorshipMinisterio de Educación y Ciencia TEC2006-11730-C03-01es
dc.description.sponsorshipJunta de Andalucía P06-TIC-01417es
dc.formatapplication/pdfes
dc.format.extent4es
dc.language.isoenges
dc.publisherIEEE Computer Societyes
dc.relation.ispartofISCAS 2008: IEEE International Symposium on Circuits and Systems (2008), p 652-655
dc.rightsAttribution-NonCommercial-NoDerivatives 4.0 Internacional*
dc.rights.urihttp://creativecommons.org/licenses/by-nc-nd/4.0/*
dc.titleFully Digital AER Convolution Chip for Vision Processinges
dc.typeinfo:eu-repo/semantics/conferenceObjectes
dcterms.identifierhttps://ror.org/03yxnpp24
dc.type.versioninfo:eu-repo/semantics/submittedVersiones
dc.rights.accessRightsinfo:eu-repo/semantics/openAccesses
dc.contributor.affiliationUniversidad de Sevilla. Departamento de Arquitectura y Tecnología de Computadoreses
dc.contributor.affiliationUniversidad de Sevilla. Departamento de Electrónica y Electromagnetismoes
dc.relation.projectIDIST-2001-34124 (CAVIAR)es
dc.relation.projectIDTIC-2003-08164-C03-01es
dc.relation.projectIDTEC2006-11730-C03-01es
dc.relation.projectIDP06-TIC-01417es
dc.relation.publisherversionhttps://ieeexplore.ieee.org/document/4541502es
dc.identifier.doi10.1109/ISCAS.2008.4541502es
dc.publication.initialPage652es
dc.publication.endPage655es
dc.eventtitleISCAS 2008: IEEE International Symposium on Circuits and Systemses
dc.eventinstitutionSeattle, USAes
dc.relation.publicationplaceNew York, USAes
dc.contributor.funderEuropean Union (UE)es
dc.contributor.funderComisión Interministerial de Ciencia y Tecnología (CICYT). Españaes
dc.contributor.funderMinisterio de Educación y Ciencia (MEC). Españaes
dc.contributor.funderJunta de Andalucíaes

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