Author profile: Avedillo de Juan, María José
Data
| Name | Avedillo de Juan, María José |
| Department | Electrónica y Electromagnetismo |
| Knowledge area | Electrónica |
| Professional category | Catedrática de Universidad |
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Items
35
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Visits
2104
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1643
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Master's Final Project
 Diseño de sistemas empotrados para aplicaciones de procesado de imagen y vídeo sobre FPGAs usando Vivado SDSoC
(2019-09-01)
El procesado de imagen y vídeo es un campo que tiene una amplia área de aplicaciones, abarcando desde la automatización ... |
Article
Power and Speed Evaluation of Hyper-FET Circuits
(2019-01-01)
Many emerging devices are currently being explored as potential alternatives to complementary metal–oxide–semiconductor ... |
PhD Thesis
Desarrollo y evaluación de arquitecturas lógicas basadas en Nanopipeline.
(2018-07-17)
El potencial de la lógica dinámica, con sus fases de precarga y evaluación es una solución muy estudiada y aplicada, para ... |
Presentation
Exploring logic architectures suitable for TFETs devices
(Institute of Electrical and Electronics Engineers, 2017-01-01)
Tunnel transistors are steep subthreshold slope devices suitable for low voltage operation so being potential candidates ... |
Article
Comparison of TFETs and CMOS using optimal design points for power-speed trade-offs
(Institute of Electrical and Electronics Engineers, 2017-01-01)
Tunnel transistors are one of the most attractive steep subthreshold slope devices currently being investigated as a means ... |
Article
Insights Into the Operation of Hyper-FET-Based Circuits
(Institute of Electrical and Electronics Engineers, 2017-01-01)
Devices combining transistors and phase transition materials are being investigated to obtain steep switching and a boost ... |
Article
Reducing the Impact of Reverse Currents in Tunnel FET Rectifiers for Energy Harvesting Applications
(Institute of Electrical and Electronics Engineers, 2017-01-01)
RF to DC passive rectifiers can benefit from the superior performance at low voltage of tunnel transistors. They have shown ... |
Presentation
Complementary tunnel gate topology to reduce crosstalk effects
(Institute of Electrical and Electronics Engineers (IEEE), 2017-01-01)
Tunnel transistors are one of the most attractive steep subthreshold slope devices which are being investigated to overcome ... |
Presentation
Improving robustness of dynamic logic based pipelines
(Institute of Electrical and Electronics Engineers, 2016-01-01)
Domino dynamic circuits are widely used in critical parts of high performance systems. In this paper we show that, in ... |
Presentation
Assessing application areas for tunnel transistor technologies
(Institute of Electrical and Electronics Engineers (IEEE), 2016-01-01)
Tunnel transistors are one of the most attractive steep subthreshold slope devices currently being investigated as a means ... |
Article
Comparative Analysis of Projected Tunnel and CMOS Transistors for Different Logic Application Areas
(Institute of Electrical and Electronics Engineers, 2016-01-01)
In this paper, five projected tunnel FET (TFET) technologies are evaluated and compared with MOSFET and FinFET transistors ... |
Article
Improving speed of tunnel FETs logic circuits
(Institute of Electrical and Electronics Engineers, 2015-01-01)
Tunnel transistors are one of the most attractive steep subthreshold slope devices which are being investigating to overcome ... |
Presentation
DOE based high-performance gate-level pipelines
(Institute of Electrical and Electronics Engineers, 2014-01-01)
Domino dynamic circuits are widely used in critical parts of high performance systems. In this paper we show that in ... |
Article
Experimental Validation of a Two-Phase Clock Scheme for Fine-Grained Pipelined Circuits Based on Monostable to Bistable Logic Elements
(Institute of Electrical and Electronics Engineers, 2014-01-01)
Abstract: Research on fine-grained pipelines can be a way to obtain high-performance applications. Monostable to bistable ... |
Presentation
Bifurcation Diagrams in MOS-NDR Frequency Divider Circuits
(Instituto Nacional de Astrofísica, Óptica y Electrónica; Universidad de Sevilla, 2012-03-01)
The behavior of a circuit able to implement frequency division is studied. It is composed of a block with an IV characteristic ... |
Article
Domino inspired MOBILE networks
(Institute of Electrical and Electronics Engineers, 2012-01-01)
MOBILE networks can be operated in a gate-level pipelined fashion allowing high through-output. If MOBILE gates are directly ... |
Article
Two-phase RTD-CMOS pipelined circuits
(Institute of Electrical and Electronics Engineers, 2012-01-01)
MOnostable-BIstable Logic Element (MOBILE) networks can be operated in a gate-level pipelined fashion (nanopipeline) ... |
PhD Thesis
Diseño lógico de circuitos digitales usando dispositivos con característica NDR
(2011-02-04)
En esta tesis doctoral se han desarrollado técnicas de diseño para circuitos electrónicos integrados que empleen dispositivos ... |
Article
Improved nanopipelined RTD adder using generalized threshold gates
(Institute of Electrical and Electronics Engineers, 2011-01-01)
Many logic circuit applications of Resonant Tunneling Diodes are based on the MOnostable-BIstable Logic Element (MOBILE). ... |
Article
Simplified single-phase clock scheme for MOBILE networks
(Institute of Electrical and Electronics Engineers, 2011-01-01)
MOBILE networks can be operated in a gate-level pipelined fashion allowing high through-output. If MOBILE gates are directly ... |
Article
RTD-CMOS pipelined networks for reduced power consumption
(Institute of Electrical and Electronics Engineers, 2011-01-01)
The incorporation of resonant tunneling diodes (RTDs) into III/V transistor technologies has shown an improved circuit ... |
Presentation
Redes MOBILE MOS-NDR operando con reloj de una fase
(2010-01-01)
La existencia de dispositivos con una característica I-V que exhibe una resistencia diferencial negativa (Negative ... |
Presentation
RTD based logic circuits using generalized threshold gates
(2008-01-01)
Many logic circuit applications of Resonant Tunneling Diodes are based on the MOnostable-BIstable Logic Element (MOBILE). ... |
Presentation
Using multi-threshold threshold gates in rtd-based logic design. A case study
(Laboratoire TIMA, 2007-01-01)
The basic building blocks for Resonant Tunnelling Diode (RTD) logic circuits are Threshold Gates (TGs) instead of the ... |
Presentation
Holding Dissapearance in RTD-based Quantizers
(Laboratoire TIMA, 2007-01-01)
Multiple-valued Logic (MVL) circuits are one of the most attractive applications of the Monostable-to-Multistable transition ... |
| PhD Thesis |
Article
COPAS: A New Algorithm for the Partial Input Encoding Problem
(Hindawi Publishing Corporation, 2002-01-01)
Frequently, the logic designer deals with functions with symbolic input variables. The binary encoding of such symbols ... |
Article
A practical floating-gate Muller-C element using vMOS threshold gates
(Institute of Electrical and Electronics Engineers, 2001-01-01)
This paper presents the rationale for vMOS-based realizations of digital circuits when logic design techniques based on ... |
Article
Efficient realization of a threshold voter for self-purging redundancy
(Springer, 2001-01-01)
The self-purging technique is not commonly used mainly due to the lack of practical implementations of its key component, ... |
Article
Nu MOS-based sorter for arithmetic applications
(2000-01-01)
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Article
νMOS-based sorter for arithmetic applications
(Hindawi Publishing Corporation, 2000-01-01)
The capabilities of the conceptual link between threshold gates and sorting networks are explored by implementing some ... |
Article
Sorting networks implemented as νMOS circuits
(Institute of Electrical and Electronics Engineers, 1998-01-01)
A new realisation for n-input sorters is presented. Resorting to the neuron-MOS (νMOS) concept and to an adequate electrical scheme, a compact and efficient implementation is obtained. |
Article
State merging and state splitting via state assignment: a new FSM synthesis algorithm
(Institute of Electrical and Electronics Engineers, 1994-01-01)
The authors describe a state assignment algorithm for FSMs which produces an assignment of non-necessarily distinct, and ... |
PhD Thesis
Una aproximación al diseño óptimo de máquinas de estados finitos
(1992-01-01)
En los Capítulos 2 y 3 se aborda el diseño lógico FSMs. En el primero de ellos estudiamos el problema de la reducción del ... |
Article
Efficient state reduction methods for PLA-based sequential circuits
(Institute of Electrical and Electronics Engineers, 1992-01-01)
Experiences with heuristics for the state reduction of finite-state machines are presented and two new heuristic algorithms ... |