Data

NameAvedillo de Juan, María José
DepartmentElectrónica y Electromagnetismo
Knowledge areaElectrónica
Professional categoryCatedrática de Universidad
E-mailRequest
         

  Statistics

  • Items

    35

  • Visits

    2104

  • Downloads

    1643

  Publications

 

Master's Final Project
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Diseño de sistemas empotrados para aplicaciones de procesado de imagen y vídeo sobre FPGAs usando Vivado SDSoC

Avedillo de Juan, María José; Sánchez Solano, Santiago; Pino Roldán, Roberto Joaquín del (2019-09-01)
El procesado de imagen y vídeo es un campo que tiene una amplia área de aplicaciones, abarcando desde la automatización ...
Article
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Power and Speed Evaluation of Hyper-FET Circuits

Núñez Martínez, Juan; Avedillo de Juan, María José (2019-01-01)
Many emerging devices are currently being explored as potential alternatives to complementary metal–oxide–semiconductor ...
PhD Thesis
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Desarrollo y evaluación de arquitecturas lógicas basadas en Nanopipeline.

Avedillo de Juan, María José; Núñez Martínez, Juan; Quintero Álvarez, Héctor Javier (2018-07-17)
El potencial de la lógica dinámica, con sus fases de precarga y evaluación es una solución muy estudiada y aplicada, para ...
Presentation
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Exploring logic architectures suitable for TFETs devices

Nuñez Martínez, Juan; Avedillo de Juan, María José (Institute of Electrical and Electronics Engineers, 2017-01-01)
Tunnel transistors are steep subthreshold slope devices suitable for low voltage operation so being potential candidates ...
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Comparison of TFETs and CMOS using optimal design points for power-speed trade-offs

Nuñez Martínez, Juan; Avedillo de Juan, María José (Institute of Electrical and Electronics Engineers, 2017-01-01)
Tunnel transistors are one of the most attractive steep subthreshold slope devices currently being investigated as a means ...
Article
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Insights Into the Operation of Hyper-FET-Based Circuits

Avedillo de Juan, María José; Nuñez Martínez, Juan (Institute of Electrical and Electronics Engineers, 2017-01-01)
Devices combining transistors and phase transition materials are being investigated to obtain steep switching and a boost ...
Article
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Reducing the Impact of Reverse Currents in Tunnel FET Rectifiers for Energy Harvesting Applications

Nuñez Martínez, Juan; Avedillo de Juan, María José (Institute of Electrical and Electronics Engineers, 2017-01-01)
RF to DC passive rectifiers can benefit from the superior performance at low voltage of tunnel transistors. They have shown ...
Presentation
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Complementary tunnel gate topology to reduce crosstalk effects

Nuñez Martínez, Juan; Avedillo de Juan, María José (Institute of Electrical and Electronics Engineers (IEEE), 2017-01-01)
Tunnel transistors are one of the most attractive steep subthreshold slope devices which are being investigated to overcome ...
Presentation
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Improving robustness of dynamic logic based pipelines

Quintero Álvarez, Héctor Javier; Avedillo de Juan, María José; Nuñez Martínez, Juan (Institute of Electrical and Electronics Engineers, 2016-01-01)
Domino dynamic circuits are widely used in critical parts of high performance systems. In this paper we show that, in ...
Presentation
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Assessing application areas for tunnel transistor technologies

Avedillo de Juan, María José; Nuñez Martínez, Juan (Institute of Electrical and Electronics Engineers (IEEE), 2016-01-01)
Tunnel transistors are one of the most attractive steep subthreshold slope devices currently being investigated as a means ...
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Comparative Analysis of Projected Tunnel and CMOS Transistors for Different Logic Application Areas

Nuñez Martínez, Juan; Avedillo de Juan, María José (Institute of Electrical and Electronics Engineers, 2016-01-01)
In this paper, five projected tunnel FET (TFET) technologies are evaluated and compared with MOSFET and FinFET transistors ...
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Improving speed of tunnel FETs logic circuits

Avedillo de Juan, María José; Nuñez Martínez, Juan (Institute of Electrical and Electronics Engineers, 2015-01-01)
Tunnel transistors are one of the most attractive steep subthreshold slope devices which are being investigating to overcome ...
Presentation
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DOE based high-performance gate-level pipelines

Nuñez Martínez, Juan; Avedillo de Juan, María José; Quintero Álvarez, Héctor Javier (Institute of Electrical and Electronics Engineers, 2014-01-01)
Domino dynamic circuits are widely used in critical parts of high performance systems. In this paper we show that in ...
Article
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Experimental Validation of a Two-Phase Clock Scheme for Fine-Grained Pipelined Circuits Based on Monostable to Bistable Logic Elements

Nuñez Martínez, Juan; Avedillo de Juan, María José; Quintana Toledo, José María (Institute of Electrical and Electronics Engineers, 2014-01-01)
Abstract: Research on fine-grained pipelines can be a way to obtain high-performance applications. Monostable to bistable ...
Presentation
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Bifurcation Diagrams in MOS-NDR Frequency Divider Circuits

Núñez Martínez, Juan; Avedillo de Juan, María José; Quintana Toledo, José María (Instituto Nacional de Astrofísica, Óptica y Electrónica; Universidad de Sevilla, 2012-03-01)
The behavior of a circuit able to implement frequency division is studied. It is composed of a block with an IV characteristic ...
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Domino inspired MOBILE networks

Nuñez Martínez, Juan; Avedillo de Juan, María José; Quintana Toledo, José María (Institute of Electrical and Electronics Engineers, 2012-01-01)
MOBILE networks can be operated in a gate-level pipelined fashion allowing high through-output. If MOBILE gates are directly ...
Article
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Two-phase RTD-CMOS pipelined circuits

Nuñez Martínez, Juan; Avedillo de Juan, María José; Quintana Toledo, José María (Institute of Electrical and Electronics Engineers, 2012-01-01)
MOnostable-BIstable Logic Element (MOBILE) networks can be operated in a gate-level pipelined fashion (nanopipeline) ...
PhD Thesis
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Diseño lógico de circuitos digitales usando dispositivos con característica NDR

Quintana Toledo, José María; Avedillo de Juan, María José; Núñez Martínez, Juan (2011-02-04)
En esta tesis doctoral se han desarrollado técnicas de diseño para circuitos electrónicos integrados que empleen dispositivos ...
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Improved nanopipelined RTD adder using generalized threshold gates

Pettenghi Roldán, Héctor; Avedillo de Juan, María José; Quintana Toledo, José María (Institute of Electrical and Electronics Engineers, 2011-01-01)
Many logic circuit applications of Resonant Tunneling Diodes are based on the MOnostable-BIstable Logic Element (MOBILE). ...
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Simplified single-phase clock scheme for MOBILE networks

Núñez Martínez, Juan; Quintana Toledo, José María; Avedillo de Juan, María José (Institute of Electrical and Electronics Engineers, 2011-01-01)
MOBILE networks can be operated in a gate-level pipelined fashion allowing high through-output. If MOBILE gates are directly ...
Article
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RTD-CMOS pipelined networks for reduced power consumption

Nuñez Martínez, Juan; Avedillo de Juan, María José; Quintana Toledo, José María (Institute of Electrical and Electronics Engineers, 2011-01-01)
The incorporation of resonant tunneling diodes (RTDs) into III/V transistor technologies has shown an improved circuit ...
Presentation
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Redes MOBILE MOS-NDR operando con reloj de una fase

Nuñez Martínez, Juan; Avedillo de Juan, María José; Quintana Toledo, José María (2010-01-01)
La existencia de dispositivos con una característica I-V que exhibe una resistencia diferencial negativa (Negative ...
Presentation
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RTD based logic circuits using generalized threshold gates

Pettenghi Roldán, Héctor; Avedillo de Juan, María José; Quintana Toledo, José María (2008-01-01)
Many logic circuit applications of Resonant Tunneling Diodes are based on the MOnostable-BIstable Logic Element (MOBILE). ...
Presentation
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Using multi-threshold threshold gates in rtd-based logic design. A case study

Pettenghi Roldán, Héctor; Avedillo de Juan, María José; Quintana Toledo, José María (Laboratoire TIMA, 2007-01-01)
The basic building blocks for Resonant Tunnelling Diode (RTD) logic circuits are Threshold Gates (TGs) instead of the ...
Presentation
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Holding Dissapearance in RTD-based Quantizers

Nuñez Martínez, Juan; Quintana Toledo, José María; Avedillo de Juan, María José (Laboratoire TIMA, 2007-01-01)
Multiple-valued Logic (MVL) circuits are one of the most attractive applications of the Monostable-to-Multistable transition ...
PhD Thesis
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Algoritmos de codificación binaria de símbolos para la síntesis lógica de circuitos integrados digitales

Avedillo de Juan, María José; Quintana Toledo, José María; Martínez Pérez, Manuel (2003-03-30)
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COPAS: A New Algorithm for the Partial Input Encoding Problem

Martínez, Manuel; Avedillo de Juan, María José; Quintana Toledo, José María; Huertas Díaz, José Luis (Hindawi Publishing Corporation, 2002-01-01)
Frequently, the logic designer deals with functions with symbolic input variables. The binary encoding of such symbols ...
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A practical floating-gate Muller-C element using vMOS threshold gates

Rodríguez Villegas, Esther; Huertas Sánchez, Gloria; Avedillo de Juan, María José; Quintana Toledo, José María; Rueda Rueda, Adoración (Institute of Electrical and Electronics Engineers, 2001-01-01)
This paper presents the rationale for vMOS-based realizations of digital circuits when logic design techniques based on ...
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Efficient realization of a threshold voter for self-purging redundancy

Quintana Toledo, José María; Avedillo de Juan, María José; Huertas Díaz, José Luis (Springer, 2001-01-01)
The self-purging technique is not commonly used mainly due to the lack of practical implementations of its key component, ...
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Nu MOS-based sorter for arithmetic applications

Rueda Rueda, Adoración; Rodríguez Villegas, Esther; Quintana Toledo, José María; Avedillo de Juan, María José; Huertas Sánchez, Gloria (2000-01-01)
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νMOS-based sorter for arithmetic applications

Rodríguez Villegas, Esther; Avedillo de Juan, María José; Quintana Toledo, José María; Huertas Sánchez, Gloria; Rueda Rueda, Adoración (Hindawi Publishing Corporation, 2000-01-01)
The capabilities of the conceptual link between threshold gates and sorting networks are explored by implementing some ...
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Sorting networks implemented as νMOS circuits

Rodríguez Villegas, Esther; Quintana Toledo, José María; Avedillo de Juan, María José; Rueda Rueda, Adoración (Institute of Electrical and Electronics Engineers, 1998-01-01)
A new realisation for n-input sorters is presented. Resorting to the neuron-MOS (νMOS) concept and to an adequate electrical scheme, a compact and efficient implementation is obtained.
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State merging and state splitting via state assignment: a new FSM synthesis algorithm

Avedillo de Juan, María José; Quintana Toledo, José María; Huertas Díaz, José Luis (Institute of Electrical and Electronics Engineers, 1994-01-01)
The authors describe a state assignment algorithm for FSMs which produces an assignment of non-necessarily distinct, and ...
PhD Thesis
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Una aproximación al diseño óptimo de máquinas de estados finitos

Huertas Díaz, José Luis; Quintana Toledo, José María; Avedillo de Juan, María José (1992-01-01)
En los Capítulos 2 y 3 se aborda el diseño lógico FSMs. En el primero de ellos estudiamos el problema de la reducción del ...
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Efficient state reduction methods for PLA-based sequential circuits

Avedillo de Juan, María José; Quintana Toledo, José María; Huertas Díaz, José Luis (Institute of Electrical and Electronics Engineers, 1992-01-01)
Experiences with heuristics for the state reduction of finite-state machines are presented and two new heuristic algorithms ...