Author profile: Avedillo de Juan, María José
Institutional data
| Name | Avedillo de Juan, María José |
| Department | Electrónica y Electromagnetismo |
| Knowledge area | Electrónica |
| Professional category | Catedrática de Universidad |
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Statistics
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No. publications
46
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No. visits
3636
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No. downloads
3771
| Publications |
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Article
 Effect of Device Mismatches in Differential Oscillatory Neural NetworksEffect of Device Mismatches in Differential Oscillatory Neural Networks
(IEEE, 2023-02-01)
Analog implementation of Oscillatory Neural Networks (ONNs) has the potential to implement fast and ultra-low-power computing ... |
Article
How Frequency Injection Locking Can Train Oscillatory Neural Networks to Compute in PhaseHow Frequency Injection Locking Can Train Oscillatory Neural Networks to Compute in Phase
(IEEE, 2022-01-01)
Brain-inspired computing employs devices and architectures that emulate biological functions for more adaptive and ... |
Master's Final Project
Sistema de reconocimiento de imágenes sobre FPGA para aplicaciones de visión artificialSistema de reconocimiento de imágenes sobre FPGA para aplicaciones de visión artificial
(2022-01-01)
Con el transcurrir de los años han surgido numerosas aplicaciones en campos muy diversos, como la medicina, la seguridad ... |
Article
Oscillatory Neural Networks Using VO2 Based Phase Encoded LogicOscillatory Neural Networks Using VO2 Based Phase Encoded Logic
(Frontiers Media, 2021-01-01)
Nano-oscillators based on phase-transition materials are being explored for the implementation of different non-conventional ... |
Article
Hardware Implementation of Differential Oscillatory Neural Networks Using VO 2-Based Oscillators and Memristor-Bridge CircuitsHardware Implementation of Differential Oscillatory Neural Networks Using VO 2-Based Oscillators and Memristor-Bridge Circuits
(Frontiers Media, 2021-01-01)
Oscillatory Neural Networks (ONNs) are currently arousing interest in the research community for their potential to implement ... |
Article
Digital Implementation of Oscillatory Neural Network for Image Recognition ApplicationsDigital Implementation of Oscillatory Neural Network for Image Recognition Applications
(Frontiers Media, 2021-01-01)
Computing paradigm based on von Neuman architectures cannot keep up with the ever-increasing data growth (also called “data ... |
Article
Hybrid-Phase-Transition FET Devices for Logic ComputationHybrid-Phase-Transition FET Devices for Logic Computation
(IEEE, 2020-01-01)
Hybrid-phase-transition FETs (HyperFETs), built by connecting a phase transition material (PTM) to the source terminal of ... |
Article
Phase Transition Device for Phase StoringPhase Transition Device for Phase Storing
(IEEE, 2020-01-01)
Nano-oscillators based on phase transitions materials (PTM) are being explored for the implementation of different ... |
Master's Final Project
Diseño de sistemas empotrados para aplicaciones de procesado de imagen y vídeo sobre FPGAs usando Vivado SDSoCDiseño de sistemas empotrados para aplicaciones de procesado de imagen y vídeo sobre FPGAs usando Vivado SDSoC
(2019-09-01)
El procesado de imagen y vídeo es un campo que tiene una amplia área de aplicaciones, abarcando desde la automatización ... |
Article
Power and Speed Evaluation of Hyper-FET CircuitsPower and Speed Evaluation of Hyper-FET Circuits
(2019-01-01)
Many emerging devices are currently being explored as potential alternatives to complementary metal–oxide–semiconductor ... |
PhD Thesis
Desarrollo y evaluación de arquitecturas lógicas basadas en Nanopipeline.Desarrollo y evaluación de arquitecturas lógicas basadas en Nanopipeline.
(2018-07-17)
El potencial de la lógica dinámica, con sus fases de precarga y evaluación es una solución muy estudiada y aplicada, para ... |
Article
Phase Transition FETs for Improved Dynamic Logic GatesPhase Transition FETs for Improved Dynamic Logic Gates
(IEEE, 2018-01-01)
Transistors incorporating phase change materials (Phase Change FETs) are being investigated to obtain steep switching and ... |
Article
Impact of the RT-level architecture on the power performance of tunnel transistor circuitsImpact of the RT-level architecture on the power performance of tunnel transistor circuits
(Wiley, 2018-01-01)
Tunnel field-effect transistors (TFETs) are one of the most attractive steep subthreshold slope devices currently being ... |
Article
Reducing the Impact of Reverse Currents in Tunnel FET Rectifiers for Energy Harvesting ApplicationsReducing the Impact of Reverse Currents in Tunnel FET Rectifiers for Energy Harvesting Applications
(Institute of Electrical and Electronics Engineers, 2017-01-01)
RF to DC passive rectifiers can benefit from the superior performance at low voltage of tunnel transistors. They have shown ... |
Presentation
Exploring logic architectures suitable for TFETs devicesExploring logic architectures suitable for TFETs devices
(Institute of Electrical and Electronics Engineers, 2017-01-01)
Tunnel transistors are steep subthreshold slope devices suitable for low voltage operation so being potential candidates ... |
Article
Insights Into the Operation of Hyper-FET-Based CircuitsInsights Into the Operation of Hyper-FET-Based Circuits
(Institute of Electrical and Electronics Engineers, 2017-01-01)
Devices combining transistors and phase transition materials are being investigated to obtain steep switching and a boost ... |
Presentation
Complementary tunnel gate topology to reduce crosstalk effectsComplementary tunnel gate topology to reduce crosstalk effects
(Institute of Electrical and Electronics Engineers (IEEE), 2017-01-01)
Tunnel transistors are one of the most attractive steep subthreshold slope devices which are being investigated to overcome ... |
Article
Comparison of TFETs and CMOS using optimal design points for power-speed trade-offsComparison of TFETs and CMOS using optimal design points for power-speed trade-offs
(Institute of Electrical and Electronics Engineers, 2017-01-01)
Tunnel transistors are one of the most attractive steep subthreshold slope devices currently being investigated as a means ... |
Article
Comparative Analysis of Projected Tunnel and CMOS Transistors for Different Logic Application AreasComparative Analysis of Projected Tunnel and CMOS Transistors for Different Logic Application Areas
(Institute of Electrical and Electronics Engineers, 2016-01-01)
In this paper, five projected tunnel FET (TFET) technologies are evaluated and compared with MOSFET and FinFET transistors ... |
Presentation
Assessing application areas for tunnel transistor technologiesAssessing application areas for tunnel transistor technologies
(Institute of Electrical and Electronics Engineers (IEEE), 2016-01-01)
Tunnel transistors are one of the most attractive steep subthreshold slope devices currently being investigated as a means ... |
Presentation
Improving robustness of dynamic logic based pipelinesImproving robustness of dynamic logic based pipelines
(Institute of Electrical and Electronics Engineers, 2016-01-01)
Domino dynamic circuits are widely used in critical parts of high performance systems. In this paper we show that, in ... |
Article
Improving speed of tunnel FETs logic circuitsImproving speed of tunnel FETs logic circuits
(Institute of Electrical and Electronics Engineers, 2015-01-01)
Tunnel transistors are one of the most attractive steep subthreshold slope devices which are being investigating to overcome ... |
Presentation
DOE based high-performance gate-level pipelinesDOE based high-performance gate-level pipelines
(Institute of Electrical and Electronics Engineers, 2014-01-01)
Domino dynamic circuits are widely used in critical parts of high performance systems. In this paper we show that in ... |
Article
Experimental Validation of a Two-Phase Clock Scheme for Fine-Grained Pipelined Circuits Based on Monostable to Bistable Logic ElementsExperimental Validation of a Two-Phase Clock Scheme for Fine-Grained Pipelined Circuits Based on Monostable to Bistable Logic Elements
(Institute of Electrical and Electronics Engineers, 2014-01-01)
Abstract: Research on fine-grained pipelines can be a way to obtain high-performance applications. Monostable to bistable ... |
Presentation
Two-Phase MOBILE Interconnection Schemes for Ultra-Grain Pipeline ApplicationsTwo-Phase MOBILE Interconnection Schemes for Ultra-Grain Pipeline Applications
(Springer, 2013-01-01)
Monostable to Bistable (MOBILE) gates are very suitable for the implementation of gate-level pipelines which can be achieved ... |
Presentation
Bifurcation Diagrams in MOS-NDR Frequency Divider CircuitsBifurcation Diagrams in MOS-NDR Frequency Divider Circuits
(Instituto Nacional de Astrofísica, Óptica y Electrónica; Universidad de Sevilla, 2012-03-01)
The behavior of a circuit able to implement frequency division is studied. It is composed of a block with an IV characteristic ... |
Article
Domino inspired MOBILE networksDomino inspired MOBILE networks
(Institute of Electrical and Electronics Engineers, 2012-01-01)
MOBILE networks can be operated in a gate-level pipelined fashion allowing high through-output. If MOBILE gates are directly ... |
Article
Two-phase RTD-CMOS pipelined circuitsTwo-phase RTD-CMOS pipelined circuits
(Institute of Electrical and Electronics Engineers, 2012-01-01)
MOnostable-BIstable Logic Element (MOBILE) networks can be operated in a gate-level pipelined fashion (nanopipeline) ... |
PhD Thesis
Diseño lógico de circuitos digitales usando dispositivos con característica NDRDiseño lógico de circuitos digitales usando dispositivos con característica NDR
(2011-02-04)
En esta tesis doctoral se han desarrollado técnicas de diseño para circuitos electrónicos integrados que empleen dispositivos ... |
Presentation
Efficient realization of RTD-CMOS logic gatesEfficient realization of RTD-CMOS logic gates
(2011-01-01)
The incorporation of Resonant Tunnel Diodes (RTDs) into III/V transistor technologies has shown an improved circuit ... |
Article
RTD-CMOS pipelined networks for reduced power consumptionRTD-CMOS pipelined networks for reduced power consumption
(Institute of Electrical and Electronics Engineers, 2011-01-01)
The incorporation of resonant tunneling diodes (RTDs) into III/V transistor technologies has shown an improved circuit ... |
Article
Improved nanopipelined RTD adder using generalized threshold gatesImproved nanopipelined RTD adder using generalized threshold gates
(Institute of Electrical and Electronics Engineers, 2011-01-01)
Many logic circuit applications of Resonant Tunneling Diodes are based on the MOnostable-BIstable Logic Element (MOBILE). ... |
Article
Simplified single-phase clock scheme for MOBILE networksSimplified single-phase clock scheme for MOBILE networks
(Institute of Electrical and Electronics Engineers, 2011-01-01)
MOBILE networks can be operated in a gate-level pipelined fashion allowing high through-output. If MOBILE gates are directly ... |
Presentation
Redes MOBILE MOS-NDR operando con reloj de una faseRedes MOBILE MOS-NDR operando con reloj de una fase
(2010-01-01)
La existencia de dispositivos con una característica I-V que exhibe una resistencia diferencial negativa (Negative ... |
Presentation
RTD based logic circuits using generalized threshold gatesRTD based logic circuits using generalized threshold gates
(2008-01-01)
Many logic circuit applications of Resonant Tunneling Diodes are based on the MOnostable-BIstable Logic Element (MOBILE). ... |
Presentation
Using multi-threshold threshold gates in rtd-based logic design. A case studyUsing multi-threshold threshold gates in rtd-based logic design. A case study
(Laboratoire TIMA, 2007-01-01)
The basic building blocks for Resonant Tunnelling Diode (RTD) logic circuits are Threshold Gates (TGs) instead of the ... |
Presentation
Holding Dissapearance in RTD-based QuantizersHolding Dissapearance in RTD-based Quantizers
(Laboratoire TIMA, 2007-01-01)
Multiple-valued Logic (MVL) circuits are one of the most attractive applications of the Monostable-to-Multistable transition ... |
| PhD Thesis |
Article
COPAS: A New Algorithm for the Partial Input Encoding ProblemCOPAS: A New Algorithm for the Partial Input Encoding Problem
(Hindawi Publishing Corporation, 2002-01-01)
Frequently, the logic designer deals with functions with symbolic input variables. The binary encoding of such symbols ... |
Article
A practical floating-gate Muller-C element using vMOS threshold gatesA practical floating-gate Muller-C element using vMOS threshold gates
(Institute of Electrical and Electronics Engineers, 2001-01-01)
This paper presents the rationale for vMOS-based realizations of digital circuits when logic design techniques based on ... |
Article
Efficient realization of a threshold voter for self-purging redundancyEfficient realization of a threshold voter for self-purging redundancy
(Springer, 2001-01-01)
The self-purging technique is not commonly used mainly due to the lack of practical implementations of its key component, ... |
Article
nu MOS-based sorter for arithmetic applicationsnu MOS-based sorter for arithmetic applications
(Hindawi Publishing Corporation, 2000-01-01)
The capabilities of the conceptual link between threshold gates and sorting networks are explored by implementing some ... |
Article
Sorting networks implemented as νMOS circuitsSorting networks implemented as νMOS circuits
(Institute of Electrical and Electronics Engineers, 1998-01-01)
A new realisation for n-input sorters is presented. Resorting to the neuron-MOS (νMOS) concept and to an adequate electrical scheme, a compact and efficient implementation is obtained. |
Article
State merging and state splitting via state assignment: a new FSM synthesis algorithmState merging and state splitting via state assignment: a new FSM synthesis algorithm
(Institute of Electrical and Electronics Engineers, 1994-01-01)
The authors describe a state assignment algorithm for FSMs which produces an assignment of non-necessarily distinct, and ... |
Article
Efficient state reduction methods for PLA-based sequential circuitsEfficient state reduction methods for PLA-based sequential circuits
(Institute of Electrical and Electronics Engineers, 1992-01-01)
Experiences with heuristics for the state reduction of finite-state machines are presented and two new heuristic algorithms ... |
PhD Thesis
Una aproximación al diseño óptimo de máquinas de estados finitosUna aproximación al diseño óptimo de máquinas de estados finitos
(1992-01-01)
En los Capítulos 2 y 3 se aborda el diseño lógico FSMs. En el primero de ellos estudiamos el problema de la reducción del ... |