Ponencia
Efficient realization of RTD-CMOS logic gates
Autor/es | Núñez Martínez, Juan
Avedillo de Juan, María José Quintana Toledo, José María |
Departamento | Universidad de Sevilla. Departamento de Electrónica y Electromagnetismo |
Fecha de publicación | 2011 |
Fecha de depósito | 2022-07-13 |
Publicado en |
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ISBN/ISSN | 978-145030667-6 |
Resumen | The incorporation of Resonant Tunnel Diodes (RTDs) into III/V transistor technologies has shown an improved circuit performance: higher circuit speed, reduced component count, and/or lowered power consumption. Currently, ... The incorporation of Resonant Tunnel Diodes (RTDs) into III/V transistor technologies has shown an improved circuit performance: higher circuit speed, reduced component count, and/or lowered power consumption. Currently, the incorporation of these devices into CMOS technologies (RTD-CMOS) is an area of active research. Although some works have focused the evaluation of the advantages of this incorporation, additional work in this direction is required. This paper compares RTD-CMOS and pure CMOS realizations of a set of logic gates which can be operated in a gate-level nanopipelined. Lower average power and energy per cycle are obtained for RTD/CMOS implementations. |
Agencias financiadoras | Ministerio de Educación y Ciencia (MEC). España European Commission (EC). Fondo Europeo de Desarrollo Regional (FEDER) Junta de Andalucía |
Identificador del proyecto | TEC2007-67245
TIC-2961 |
Cita | Núñez Martínez, J., Avedillo de Juan, M.J. y Quintana Toledo, J.M. (2011). Efficient realization of RTD-CMOS logic gates. En 21st Great lakes symposium on VLSI. |
Ficheros | Tamaño | Formato | Ver | Descripción |
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Efficient Realization.pdf | 189.7Kb | [PDF] | Ver/ | Postprint |