NombreQuintana Toledo, José María
DepartamentoElectrónica y Electromagnetismo
Área de conocimientoElectrónica
Categoría profesionalCatedrático de Universidad
Correo electrónicoSolicitar
           
  • Nº publicaciones

    29

  • Nº visitas

    2844

  • Nº descargas

    2695


 

Artículo
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Oscillatory Neural Networks Using VO2 Based Phase Encoded Logic

Núñez Martínez, Juan; Avedillo de Juan, María José; Jiménez, Manuel; Quintana Toledo, José María; Todri Sanial, Aida; Corti, Elisabetta; Karg, Siegfried; Linares Barranco, Bernabé (Frontiers Media, 2021)
Nano-oscillators based on phase-transition materials are being explored for the implementation of different non-conventional ...
Artículo
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Phase Transition Device for Phase Storing

Avedillo de Juan, María José; Quintana Toledo, José María; Núñez Martínez, Juan (IEEE, 2020)
Nano-oscillators based on phase transitions materials (PTM) are being explored for the implementation of different ...
Artículo
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Experimental Validation of a Two-Phase Clock Scheme for Fine-Grained Pipelined Circuits Based on Monostable to Bistable Logic Elements

Núñez Martínez, Juan; Avedillo de Juan, María José; Quintana Toledo, José María (Institute of Electrical and Electronics Engineers, 2014)
Abstract: Research on fine-grained pipelines can be a way to obtain high-performance applications. Monostable to bistable ...
Artículo
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Novel pipeline architectures based on Negative Differential Resistance devices

Núñez Martínez, Juan; Avedillo de Juan, María José; Quintana Toledo, José María (Elsevier, 2013)
Devices exhibiting Negative Differential Resistance (NDR) in their I-V characteristic are attractive from the design point ...
Ponencia
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Two-Phase MOBILE Interconnection Schemes for Ultra-Grain Pipeline Applications

Núñez Martínez, Juan; Avedillo de Juan, María José; Quintana Toledo, José María (Springer, 2013)
Monostable to Bistable (MOBILE) gates are very suitable for the implementation of gate-level pipelines which can be achieved ...
Ponencia
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Bifurcation Diagrams in MOS-NDR Frequency Divider Circuits

Núñez Martínez, Juan; Avedillo de Juan, María José; Quintana Toledo, José María (Instituto Nacional de Astrofísica, Óptica y Electrónica; Universidad de Sevilla, 2012)
The behavior of a circuit able to implement frequency division is studied. It is composed of a block with an IV characteristic ...
Artículo
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Domino inspired MOBILE networks

Núñez Martínez, Juan; Avedillo de Juan, María José; Quintana Toledo, José María (Institute of Electrical and Electronics Engineers, 2012)
MOBILE networks can be operated in a gate-level pipelined fashion allowing high through-output. If MOBILE gates are directly ...
Artículo
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Two-phase RTD-CMOS pipelined circuits

Núñez Martínez, Juan; Avedillo de Juan, María José; Quintana Toledo, José María (Institute of Electrical and Electronics Engineers, 2012)
MOnostable-BIstable Logic Element (MOBILE) networks can be operated in a gate-level pipelined fashion (nanopipeline) ...
Tesis Doctoral
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Diseño lógico de circuitos digitales usando dispositivos con característica NDR

Núñez Martínez, Juan; Quintana Toledo, José María; Avedillo de Juan, María José (2011)
En esta tesis doctoral se han desarrollado técnicas de diseño para circuitos electrónicos integrados que empleen dispositivos ...
Artículo
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Simplified single-phase clock scheme for MOBILE networks

Núñez Martínez, Juan; Quintana Toledo, José María; Avedillo de Juan, María José (Institute of Electrical and Electronics Engineers, 2011)
MOBILE networks can be operated in a gate-level pipelined fashion allowing high through-output. If MOBILE gates are directly ...
Artículo
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RTD-CMOS pipelined networks for reduced power consumption

Núñez Martínez, Juan; Avedillo de Juan, María José; Quintana Toledo, José María (Institute of Electrical and Electronics Engineers, 2011)
The incorporation of resonant tunneling diodes (RTDs) into III/V transistor technologies has shown an improved circuit ...
Ponencia
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Efficient realization of RTD-CMOS logic gates

Núñez Martínez, Juan; Avedillo de Juan, María José; Quintana Toledo, José María (2011)
The incorporation of Resonant Tunnel Diodes (RTDs) into III/V transistor technologies has shown an improved circuit ...
Artículo
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Improved nanopipelined RTD adder using generalized threshold gates

Pettenghi Roldán, Héctor; Avedillo de Juan, María José; Quintana Toledo, José María (Institute of Electrical and Electronics Engineers, 2011)
Many logic circuit applications of Resonant Tunneling Diodes are based on the MOnostable-BIstable Logic Element (MOBILE). ...
Ponencia
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Redes MOBILE MOS-NDR operando con reloj de una fase

Núñez Martínez, Juan; Avedillo de Juan, María José; Quintana Toledo, José María (2010)
La existencia de dispositivos con una característica I-V que exhibe una resistencia diferencial negativa (Negative ...
Artículo
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Efficient realisation of MOS-NDR threshold logic gates

Núñez Martínez, Juan; Avedillo de Juan, María José; Quintana Toledo, José María (Wiley Open Access, 2009)
A novel realisation of inverted majority gates based on a programmable MOS-NDR device is presented. A comparison, in terms ...
Artículo
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Operation limits for RTD-based MOBILE circuits

Quintana Toledo, José María; Avedillo de Juan, María José; Núñez Martínez, Juan; Pettenghi Roldán, Héctor (IEEE, 2009)
Resonant-tunneling-diode (RTD)-based monostable-bistable logic element (MOBILE) circuits operate properly in a certain ...
Ponencia
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RTD based logic circuits using generalized threshold gates

Pettenghi Roldán, Héctor; Avedillo de Juan, María José; Quintana Toledo, José María (2008)
Many logic circuit applications of Resonant Tunneling Diodes are based on the MOnostable-BIstable Logic Element (MOBILE). ...
Ponencia
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Holding Dissapearance in RTD-based Quantizers

Núñez Martínez, Juan; Quintana Toledo, José María; Avedillo de Juan, María José (Laboratoire TIMA, 2007)
Multiple-valued Logic (MVL) circuits are one of the most attractive applications of the Monostable-to-Multistable transition ...
Ponencia
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Using multi-threshold threshold gates in rtd-based logic design. A case study

Pettenghi Roldán, Héctor; Avedillo de Juan, María José; Quintana Toledo, José María (Laboratoire TIMA, 2007)
The basic building blocks for Resonant Tunnelling Diode (RTD) logic circuits are Threshold Gates (TGs) instead of the ...
Tesis Doctoral
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Algoritmos de codificación binaria de símbolos para la síntesis lógica de circuitos integrados digitales

Martínez Pérez, Manuel; Avedillo de Juan, María José; Quintana Toledo, José María (2003)
Artículo
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COPAS: A New Algorithm for the Partial Input Encoding Problem

Martínez, Manuel; Avedillo de Juan, María José; Quintana Toledo, José María; Huertas Díaz, José Luis (Hindawi Publishing Corporation, 2002)
Frequently, the logic designer deals with functions with symbolic input variables. The binary encoding of such symbols ...
Tesis Doctoral
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GELSA: un colocador flexible para circuitos integrados analógicos

Prieto Rodríguez, Juan Antonio; Rueda Rueda, Adoración; Quintana Toledo, José María (2001)
Artículo
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A practical floating-gate Muller-C element using vMOS threshold gates

Rodríguez Villegas, Esther; Huertas Sánchez, Gloria; Avedillo de Juan, María José; Quintana Toledo, José María; Rueda Rueda, Adoración (Institute of Electrical and Electronics Engineers, 2001)
This paper presents the rationale for vMOS-based realizations of digital circuits when logic design techniques based on ...
Artículo
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Efficient realization of a threshold voter for self-purging redundancy

Quintana Toledo, José María; Avedillo de Juan, María José; Huertas Díaz, José Luis (Springer, 2001)
The self-purging technique is not commonly used mainly due to the lack of practical implementations of its key component, ...
Artículo
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nu MOS-based sorter for arithmetic applications

Rodríguez Villegas, Esther; Avedillo de Juan, María José; Quintana Toledo, José María; Huertas Sánchez, Gloria; Rueda Rueda, Adoración (Hindawi Publishing Corporation, 2000)
The capabilities of the conceptual link between threshold gates and sorting networks are explored by implementing some ...
Artículo
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Sorting networks implemented as νMOS circuits

Rodríguez Villegas, Esther; Quintana Toledo, José María; Avedillo de Juan, María José; Rueda Rueda, Adoración (Institute of Electrical and Electronics Engineers, 1998)
A new realisation for n-input sorters is presented. Resorting to the neuron-MOS (νMOS) concept and to an adequate electrical scheme, a compact and efficient implementation is obtained.
Artículo
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State merging and state splitting via state assignment: a new FSM synthesis algorithm

Avedillo de Juan, María José; Quintana Toledo, José María; Huertas Díaz, José Luis (Institute of Electrical and Electronics Engineers, 1994)
The authors describe a state assignment algorithm for FSMs which produces an assignment of non-necessarily distinct, and ...
Tesis Doctoral
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Una aproximación al diseño óptimo de máquinas de estados finitos

Avedillo de Juan, María José; Huertas Díaz, José Luis; Quintana Toledo, José María (1992)
En los Capítulos 2 y 3 se aborda el diseño lógico FSMs. En el primero de ellos estudiamos el problema de la reducción del ...
Artículo
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Efficient state reduction methods for PLA-based sequential circuits

Avedillo de Juan, María José; Quintana Toledo, José María; Huertas Díaz, José Luis (Institute of Electrical and Electronics Engineers, 1992)
Experiences with heuristics for the state reduction of finite-state machines are presented and two new heuristic algorithms ...