Artículo
A practical floating-gate Muller-C element using vMOS threshold gates
Autor/es | Rodríguez Villegas, Esther
Huertas Sánchez, Gloria Avedillo de Juan, María José Quintana Toledo, José María Rueda Rueda, Adoración |
Departamento | Universidad de Sevilla. Departamento de Electrónica y Electromagnetismo |
Fecha de publicación | 2001 |
Fecha de depósito | 2018-06-19 |
Publicado en |
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Resumen | This paper presents the rationale for vMOS-based realizations of digital circuits when logic design techniques based on threshold logic gates are used. Some practical problems in the vMOS implementation of threshold gates ... This paper presents the rationale for vMOS-based realizations of digital circuits when logic design techniques based on threshold logic gates are used. Some practical problems in the vMOS implementation of threshold gates have been identified and solved. The feasibility and versatility of the proposed technique as well as its potential as a low-cost design technique for CMOS technologies have been shown by experimental results from a multiple-input Muller C-element. The proposed new realization exhibits better performance related to delay and area and power consumption than the traditional logic implementation. |
Cita | Rodríguez Villegas, E., Huertas Sánchez, G., Avedillo de Juan, M.J., Quintana Toledo, J.M. y Rueda Rueda, A. (2001). A practical floating-gate Muller-C element using vMOS threshold gates. IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, 48 (1), 102-106. |
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