dc.creator | Rodríguez Villegas, Esther | es |
dc.creator | Huertas Sánchez, Gloria | es |
dc.creator | Avedillo de Juan, María José | es |
dc.creator | Quintana Toledo, José María | es |
dc.creator | Rueda Rueda, Adoración | es |
dc.date.accessioned | 2018-06-19T13:56:36Z | |
dc.date.available | 2018-06-19T13:56:36Z | |
dc.date.issued | 2001 | |
dc.identifier.citation | Rodríguez Villegas, E., Huertas Sánchez, G., Avedillo de Juan, M.J., Quintana Toledo, J.M. y Rueda Rueda, A. (2001). A practical floating-gate Muller-C element using vMOS threshold gates. IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, 48 (1), 102-106. | |
dc.identifier.issn | 1057-7130 | es |
dc.identifier.uri | https://hdl.handle.net/11441/76324 | |
dc.description.abstract | This paper presents the rationale for vMOS-based realizations of digital circuits when logic design techniques based on threshold logic gates are used. Some practical problems in the vMOS implementation of threshold gates have been identified and solved. The feasibility and versatility of the proposed technique as well as its potential as a low-cost design technique for CMOS technologies have been shown by experimental results from a multiple-input Muller C-element. The proposed new realization exhibits better performance related to delay and area and power consumption than the traditional logic implementation. | es |
dc.format | application/pdf | es |
dc.language.iso | eng | es |
dc.publisher | Institute of Electrical and Electronics Engineers | es |
dc.relation.ispartof | IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, 48 (1), 102-106. | |
dc.rights | Attribution-NonCommercial-NoDerivatives 4.0 Internacional | * |
dc.rights.uri | http://creativecommons.org/licenses/by-nc-nd/4.0/ | * |
dc.subject | Threshold logic design | es |
dc.subject | Concurrence elements | es |
dc.subject | Neuron-MOS transistor applications | es |
dc.title | A practical floating-gate Muller-C element using vMOS threshold gates | es |
dc.type | info:eu-repo/semantics/article | es |
dcterms.identifier | https://ror.org/03yxnpp24 | |
dc.type.version | info:eu-repo/semantics/submittedVersion | es |
dc.rights.accessRights | info:eu-repo/semantics/openAccess | es |
dc.contributor.affiliation | Universidad de Sevilla. Departamento de Electrónica y Electromagnetismo | es |
dc.relation.publisherversion | http://dx.doi.org/10.1109/82.913193 | es |
dc.identifier.doi | 10.1109/82.913193 | es |
idus.format.extent | 12 p. | es |
dc.journaltitle | IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing | es |
dc.publication.volumen | 48 | es |
dc.publication.issue | 1 | es |
dc.publication.initialPage | 102 | es |
dc.publication.endPage | 106 | es |