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Ponencia
Complementary tunnel gate topology to reduce crosstalk effects
Autor/es | Núñez Martínez, Juan
Avedillo de Juan, María José |
Departamento | Universidad de Sevilla. Departamento de Electrónica y Electromagnetismo |
Fecha de publicación | 2017 |
Fecha de depósito | 2018-05-03 |
Publicado en |
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Resumen | Tunnel transistors are one of the most attractive steep
subthreshold slope devices which are being investigated to
overcome power density and energy inefficiency exhibited by
CMOS technology. There are design challenges ... Tunnel transistors are one of the most attractive steep subthreshold slope devices which are being investigated to overcome power density and energy inefficiency exhibited by CMOS technology. There are design challenges associated to their distinguishing characteristic which are being addressed. In this paper the impact of the non-symmetric conduction of tunnel transistors (TFETs) on the speed of TFETs circuits under crosstalk is analyzed and a novel topology for complementary tunnel transistors gates, which mitigates the observed performance degradation without power penalties, is described and evaluated. |
Cita | Nuñez Martínez, J. y Avedillo de Juan, M.J. (2017). Complementary tunnel gate topology to reduce crosstalk effects. En Design of Circuits and Integrated Systems (DCIS) (1-5), Granada, 23-25 November 2016: Institute of Electrical and Electronics Engineers (IEEE). |
Ficheros | Tamaño | Formato | Ver | Descripción |
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Complementary Tunnel.pdf | 110.5Kb | [PDF] | Ver/ | |