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Ponencia
Assessing application areas for tunnel transistor technologies
Autor/es | Avedillo de Juan, María José
Núñez Martínez, Juan |
Departamento | Universidad de Sevilla. Departamento de Electrónica y Electromagnetismo |
Fecha de publicación | 2016 |
Fecha de depósito | 2018-05-03 |
Publicado en |
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Resumen | Tunnel transistors are one of the most attractive steep
subthreshold slope devices currently being investigated as a
means of overcoming the power density and energy inefficiency
limitations of CMOS technology. In this ... Tunnel transistors are one of the most attractive steep subthreshold slope devices currently being investigated as a means of overcoming the power density and energy inefficiency limitations of CMOS technology. In this paper, projected tunnel transistor technologies are evaluated and compared to LP and HP versions of both conventional and FinFET CMOS in terms of their power and energy in different application areas. |
Agencias financiadoras | Ministerio de Economía y Competitividad (MINECO). España |
Identificador del proyecto | TEC2013-40670-P |
Cita | Avedillo de Juan, M.J. y Nuñez Martínez, J. (2016). Assessing application areas for tunnel transistor technologies. En Design of Circuits and Integrated Systems (DCIS) (1-6), Lisboa, 25-27 November 2015: Institute of Electrical and Electronics Engineers (IEEE). |
Ficheros | Tamaño | Formato | Ver | Descripción |
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Assessing application.pdf | 234.8Kb | [PDF] | Ver/ | |