Artículo
Impact of the RT-level architecture on the power performance of tunnel transistor circuits
Autor/es | Avedillo de Juan, María José
Núñez Martínez, Juan |
Departamento | Universidad de Sevilla. Departamento de Electrónica y Electromagnetismo |
Fecha de publicación | 2018 |
Fecha de depósito | 2022-07-07 |
Publicado en |
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Resumen | Tunnel field-effect transistors (TFETs) are one of the most attractive steep subthreshold slope devices currently being investigated as a means of overcoming the power density and energy inefficiency limitations of ... Tunnel field-effect transistors (TFETs) are one of the most attractive steep subthreshold slope devices currently being investigated as a means of overcoming the power density and energy inefficiency limitations of Complementary Metal Oxide Semiconductor (CMOS) technology. In this paper, we analyze the relationship between devices and register transfer–level architecture choices. We claim that architectural issues should be considered when evaluating this type of transistors because of the differences in delay versus supply voltage behavior exhibited by TFET logic gates with respect to CMOS gates. More specifically, the potential of pipelining and parallelism, both of which rely on lowering supply voltage, as power reduction techniques is evaluated and compared for CMOS and TFET technologies. The results obtained show significantly larger savings in power and energy per clock cycle for the TFET designs than for their CMOS counterparts, especially at low voltages. Pipelining and parallelism make it possibly to fully exploit the distinguishing characteristics of TFETs, and their relevance as competitive TFET circuit design solutions should be explored in greater depth. |
Agencias financiadoras | Ministerio de Economía y Competitividad (MINECO). España European Commission (EC). Fondo Europeo de Desarrollo Regional (FEDER) |
Identificador del proyecto | TEC2013‐40670‐P |
Cita | Avedillo de Juan, M.J. y Núñez Martínez, J. (2018). Impact of the RT-level architecture on the power performance of tunnel transistor circuits. International Journal of Circuit Theory and Applications, 46 (3), 647-655. |
Ficheros | Tamaño | Formato | Ver | Descripción |
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10.1002_cta.2398.pdf | 603.5Kb | [PDF] | Ver/ | |