Ponencia
Expandible high-order cascade ya modulator with constant, reduced systematic loss of resolution
Autor/es | Medeiro Hidalgo, Fernando
Río Fernández, Rocío del Rosa Utrera, José Manuel de la Pérez Verdú, Belén Rodríguez Vázquez, Ángel Benito |
Departamento | Universidad de Sevilla. Departamento de Electrónica y Electromagnetismo |
Fecha de publicación | 2003 |
Fecha de depósito | 2019-10-24 |
Publicado en |
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ISBN/ISSN | 0-7803-7705-2 1091-5281 |
Resumen | An arbitrary order sigma-delta modulator cascude
architecture is presented with only I-bit loss of resolution due to
scaling issues, even with single-bit quantizulion. This loss is kept
with a high overloading point, ... An arbitrary order sigma-delta modulator cascude architecture is presented with only I-bit loss of resolution due to scaling issues, even with single-bit quantizulion. This loss is kept with a high overloading point, regardless of the order. Simulations reveol that circuit imperfections can be tolerated up to 6th order, so that 90-dB SNDR can be obtained with x16 oversampling, without multi-bit quantization. |
Identificador del proyecto | 2001-34283/TAMES-2
TIC2001-0929/ADAVERE |
Cita | Medeiro Hidalgo, F., Río Fernández, R.d., Rosa Utrera, J.M.d.l., Pérez Verdú, B. y Rodríguez Vázquez, Á.B. (2003). Expandible high-order cascade ya modulator with constant, reduced systematic loss of resolution. En Proceedings of the 20th IEEE Instrumentation Technology Conference (229-231), Vail, USA: Institute of Electrical and Electronics Engineers. |
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