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High-Performance Architecture for Binary-Tree-Based Finite State Machines

 

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Acceso restringido High-Performance Architecture for Binary-Tree-Based Finite State Machines
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Author: Senhadji Navarro, Raouf
García Vargas, Ignacio
Department: Universidad de Sevilla. Departamento de Arquitectura y Tecnología de Computadores
Date: 2018
Published in: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 37 (4), 796-805.
Document type: Article
Abstract: A binary-tree-based finite state machine (BT-FSM) is a state machine with a 1-bit input signal whose state transition graph is a binary tree. BT-FSMs are useful in those application areas where searching in a binary tree is required, such as computer networks, compression, automatic control, or cryptography. This paper presents a new architecture for implementing BT-FSMs which is based on the model finite virtual state machine (FVSM). The proposed architecture has been compared with the general FVSM and conventional approaches by using both synthetic test benches and very large BT-FSMs obtained from a real application. In synthetic test benches, the average speed improvement of the proposed architecture respect to the best results of the other approaches achieves 41% (there are some cases in which the speed is more than double). In the case of the real application, the average speed improvement achieves 155%.
Cite: Senhadji Navarro, R. y García Vargas, I. (2018). High-Performance Architecture for Binary-Tree-Based Finite State Machines. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 37 (4), 796-805.
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URI: https://hdl.handle.net/11441/83470

DOI: 10.1109/TCAD.2017.2731678

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