dc.creator | Senhadji Navarro, Raouf | es |
dc.creator | García Vargas, Ignacio | es |
dc.date.accessioned | 2019-02-26T10:17:52Z | |
dc.date.available | 2019-02-26T10:17:52Z | |
dc.date.issued | 2018 | |
dc.identifier.citation | Senhadji Navarro, R. y García Vargas, I. (2018). High-Performance Architecture for Binary-Tree-Based Finite State Machines. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 37 (4), 796-805. | |
dc.identifier.issn | 0278-0070 | es |
dc.identifier.uri | https://hdl.handle.net/11441/83470 | |
dc.description.abstract | A binary-tree-based finite state machine (BT-FSM)
is a state machine with a 1-bit input signal whose state transition
graph is a binary tree. BT-FSMs are useful in those
application areas where searching in a binary tree is required,
such as computer networks, compression, automatic control, or
cryptography. This paper presents a new architecture for implementing
BT-FSMs which is based on the model finite virtual state
machine (FVSM). The proposed architecture has been compared
with the general FVSM and conventional approaches by using
both synthetic test benches and very large BT-FSMs obtained
from a real application. In synthetic test benches, the average
speed improvement of the proposed architecture respect to the
best results of the other approaches achieves 41% (there are
some cases in which the speed is more than double). In the
case of the real application, the average speed improvement
achieves 155%. | es |
dc.format | application/pdf | es |
dc.language.iso | eng | es |
dc.publisher | IEEE Computer Society | es |
dc.relation.ispartof | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 37 (4), 796-805. | |
dc.rights | Attribution-NonCommercial-NoDerivatives 4.0 Internacional | * |
dc.rights.uri | http://creativecommons.org/licenses/by-nc-nd/4.0/ | * |
dc.subject | Binary tree | es |
dc.subject | Field programmable gate array (FPGA) | es |
dc.subject | Finite state machine | es |
dc.subject | Finite virtual state machine (FVSM) | es |
dc.title | High-Performance Architecture for Binary-Tree-Based Finite State Machines | es |
dc.type | info:eu-repo/semantics/article | es |
dcterms.identifier | https://ror.org/03yxnpp24 | |
dc.type.version | info:eu-repo/semantics/submittedVersion | es |
dc.rights.accessRights | info:eu-repo/semantics/embargoedAccess | es |
dc.contributor.affiliation | Universidad de Sevilla. Departamento de Arquitectura y Tecnología de Computadores | es |
dc.date.embargoEndDate | 2020-04 | |
dc.relation.publisherversion | https://ieeexplore.ieee.org/document/7990247 | es |
dc.identifier.doi | 10.1109/TCAD.2017.2731678 | es |
idus.format.extent | 10 | es |
dc.journaltitle | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | es |
dc.publication.volumen | 37 | es |
dc.publication.issue | 4 | es |
dc.publication.initialPage | 796 | es |
dc.publication.endPage | 805 | es |