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dc.creatorSenhadji Navarro, Raoufes
dc.creatorGarcía Vargas, Ignacioes
dc.date.accessioned2019-02-26T10:17:52Z
dc.date.available2019-02-26T10:17:52Z
dc.date.issued2018
dc.identifier.citationSenhadji Navarro, R. y García Vargas, I. (2018). High-Performance Architecture for Binary-Tree-Based Finite State Machines. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 37 (4), 796-805.
dc.identifier.issn0278-0070es
dc.identifier.urihttps://hdl.handle.net/11441/83470
dc.description.abstractA binary-tree-based finite state machine (BT-FSM) is a state machine with a 1-bit input signal whose state transition graph is a binary tree. BT-FSMs are useful in those application areas where searching in a binary tree is required, such as computer networks, compression, automatic control, or cryptography. This paper presents a new architecture for implementing BT-FSMs which is based on the model finite virtual state machine (FVSM). The proposed architecture has been compared with the general FVSM and conventional approaches by using both synthetic test benches and very large BT-FSMs obtained from a real application. In synthetic test benches, the average speed improvement of the proposed architecture respect to the best results of the other approaches achieves 41% (there are some cases in which the speed is more than double). In the case of the real application, the average speed improvement achieves 155%.es
dc.formatapplication/pdfes
dc.language.isoenges
dc.publisherIEEE Computer Societyes
dc.relation.ispartofIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 37 (4), 796-805.
dc.rightsAttribution-NonCommercial-NoDerivatives 4.0 Internacional*
dc.rights.urihttp://creativecommons.org/licenses/by-nc-nd/4.0/*
dc.subjectBinary treees
dc.subjectField programmable gate array (FPGA)es
dc.subjectFinite state machinees
dc.subjectFinite virtual state machine (FVSM)es
dc.titleHigh-Performance Architecture for Binary-Tree-Based Finite State Machineses
dc.typeinfo:eu-repo/semantics/articlees
dc.type.versioninfo:eu-repo/semantics/submittedVersiones
dc.rights.accessrightsinfo:eu-repo/semantics/embargoAccesses
dc.contributor.affiliationUniversidad de Sevilla. Departamento de Arquitectura y Tecnología de Computadoreses
dc.date.embargoEndDate2020-04
dc.relation.publisherversionhttps://ieeexplore.ieee.org/document/7990247es
dc.identifier.doi10.1109/TCAD.2017.2731678es
idus.format.extent10es
dc.journaltitleIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systemses
dc.publication.volumen37es
dc.publication.issue4es
dc.publication.initialPage796es
dc.publication.endPage805es

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Attribution-NonCommercial-NoDerivatives 4.0 Internacional
Except where otherwise noted, this item's license is described as: Attribution-NonCommercial-NoDerivatives 4.0 Internacional