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Effect of Clock Jitter Error on the Performance Degradation of Multi-bit Continuous-Time ΣΔ Modulators With NRZ DAC

 

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Opened Access Effect of Clock Jitter Error on the Performance Degradation of Multi-bit Continuous-Time ΣΔ Modulators With NRZ DAC
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Author: Tortosa Navas, Ramón
Rosa Utrera, José Manuel de la
Rodríguez Vázquez, Ángel Benito
Fernández Fernández, Francisco Vidal
Department: Universidad de Sevilla. Departamento de Electrónica y Electromagnetismo
Date: 2005
Published in: Conference on Design of Circuits and Integrated Systems (2005), p 1-6
Document type: Presentation
Abstract: This paper analyses the effect of the clock jitter error in multi-bit continuous-time ΣΔ modulators with non-return-to-zero feedback waveform. Derived expressions show that the jitter-induced noise power can be separated into two main components: one that depends on the modulator loop filter transfer function and the other one due to the input signal parameters, i.e amplitude and frequency. The latter component, not considered in previous approaches, allows us to accurately predict the resolution loss caused by jitter, showing effects not taken into account up to now in literature which are specially critical in broadband telecom applications. Moreover, the use of state-space formulation makes the analysis quite general and applicable to either cascade or single-loop architectures. Time-domain simulations of several modulator topologies intended for VDSL application are given to validate the presented analysis.
Cite: Tortosa Navas, R., Rosa Utrera, J.M.d.l., Rodríguez Vázquez, Á.B. y Fernández Fernández, F.V. (2005). Effect of Clock Jitter Error on the Performance Degradation of Multi-bit Continuous-Time ΣΔ Modulators With NRZ DAC. En Conference on Design of Circuits and Integrated Systems, Lisboa (Portugal).
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URI: https://hdl.handle.net/11441/79958

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