dc.creator | Avedillo de Juan, María José | es |
dc.creator | Núñez Martínez, Juan | es |
dc.date.accessioned | 2018-05-03T14:45:35Z | |
dc.date.available | 2018-05-03T14:45:35Z | |
dc.date.issued | 2016 | |
dc.identifier.citation | Avedillo de Juan, M.J. y Nuñez Martínez, J. (2016). Assessing application areas for tunnel transistor technologies. En Design of Circuits and Integrated Systems (DCIS) (1-6), Lisboa, 25-27 November 2015: Institute of Electrical and Electronics Engineers (IEEE). | |
dc.identifier.uri | https://hdl.handle.net/11441/73992 | |
dc.description.abstract | Tunnel transistors are one of the most attractive steep
subthreshold slope devices currently being investigated as a
means of overcoming the power density and energy inefficiency
limitations of CMOS technology. In this paper, projected tunnel
transistor technologies are evaluated and compared to LP and
HP versions of both conventional and FinFET CMOS in terms of
their power and energy in different application areas. | es |
dc.description.sponsorship | Ministerio de Economía y Competitividad FEDER TEC2013-40670-P | es |
dc.format | application/pdf | es |
dc.language.iso | eng | es |
dc.publisher | Institute of Electrical and Electronics Engineers (IEEE) | es |
dc.relation.ispartof | Design of Circuits and Integrated Systems (DCIS) (2016), pp. 1-6. | |
dc.rights | Atribución-NoComercial-SinDerivadas 3.0 Estados Unidos de América | * |
dc.rights.uri | http://creativecommons.org/licenses/by-nc-nd/4.0/ | * |
dc.subject | Tunnel transistors | es |
dc.subject | Steep subthreshold slope | es |
dc.subject | Low power | es |
dc.subject | Energy efficieny | es |
dc.subject | Low supply voltage | es |
dc.title | Assessing application areas for tunnel transistor technologies | es |
dc.type | info:eu-repo/semantics/conferenceObject | es |
dcterms.identifier | https://ror.org/03yxnpp24 | |
dc.type.version | info:eu-repo/semantics/acceptedVersion | es |
dc.rights.accessRights | info:eu-repo/semantics/openAccess | es |
dc.contributor.affiliation | Universidad de Sevilla. Departamento de Electrónica y Electromagnetismo | es |
dc.relation.projectID | TEC2013-40670-P | es |
dc.relation.publisherversion | https://doi.org/10.1109/DCIS.2015.7388581 | es |
dc.identifier.doi | 10.1109/DCIS.2015.7388581 | es |
idus.format.extent | 6 p. | es |
dc.publication.initialPage | 1 | es |
dc.publication.endPage | 6 | es |
dc.eventtitle | Design of Circuits and Integrated Systems (DCIS) | es |
dc.eventinstitution | Lisboa, 25-27 November 2015 | es |
dc.contributor.funder | Ministerio de Economía y Competitividad (MINECO). España | |