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dc.creatorBarragán-Villarejo, Manueles
dc.creatorLéger, Gildases
dc.creatorRueda Rueda, Adoraciónes
dc.creatorHuertas Díaz, José Luises
dc.date.accessioned2017-11-22T18:08:13Z
dc.date.available2017-11-22T18:08:13Z
dc.date.issued2011-01-06
dc.identifier.citationBarragán Villarejo, M., Leger Leger, G., Rueda Rueda, A. y Huertas Díaz, J.L. (2011). Alternate test of LNAs through ensemble learning of on-chip digital envelope signatures. Journal of Electronic Testing, 27 (3), 277-288.
dc.identifier.issn0923-8174 (impreso)es
dc.identifier.urihttp://hdl.handle.net/11441/66491
dc.description.abstractThis paper presents a novel and low-cost methodology for testing embedded Low Noise Amplifiers (LNAs). It is based on the detection and analysis of the response envelope of the Device Under Test (DUT) to a two-tone input signal. The envelope signal is processed to obtain a digital signature sensitive to key specifications of the DUT. An optimized regression model based on ensemble learning is used to relate the digital signatures to the target specifications. A new Figure of Merit (FOM) is proposed to evaluate the prediction accuracy of the statistical model, and a demonstrator has been developed to prove the feasibility of the approach. This demonstrator features a 2.445 GHz low-power LNA and a simple envelope detector, and has been developed in a 90 nm CMOS technology. Post-layout simulations are provided to verify the functionality of the proposed test technique.es
dc.description.sponsorshipGobierno de España TEC2007-68072/MIC, TSI-020400-2008-71/MEDEA+2A105, CATRENE CT302es
dc.description.sponsorshipJunta de Andalucia P09-TIC-5386es
dc.formatapplication/pdfes
dc.language.isoenges
dc.publisherSpringeres
dc.relation.ispartofJournal of Electronic Testing, 27 (3), 277-288.
dc.rightsAttribution-NonCommercial-NoDerivatives 4.0 Internacional*
dc.rights.urihttp://creativecommons.org/licenses/by-nc-nd/4.0/*
dc.titleAlternate test of LNAs through ensemble learning of on-chip digital envelope signatureses
dc.typeinfo:eu-repo/semantics/articlees
dcterms.identifierhttps://ror.org/03yxnpp24
dc.type.versioninfo:eu-repo/semantics/submittedVersiones
dc.rights.accessRightsinfo:eu-repo/semantics/openAccesses
dc.contributor.affiliationUniversidad de Sevilla. Departamento de Ingeniería Eléctricaes
dc.contributor.affiliationUniversidad de Sevilla. Departamento de Electrónica y Electromagnetismoes
dc.relation.projectIDTEC2007-68072/MICes
dc.relation.projectIDTSI-020400-2008-71/MEDEA+2A105es
dc.relation.projectIDCATRENE CT302es
dc.relation.projectIDP09-TIC-5386es
dc.relation.publisherversionhttp://dx.doi.org/10.1007/s10836-010-5193-4es
dc.identifier.doi10.1007/s10836-010-5193-4es
idus.format.extent28 p.es
dc.journaltitleJournal of Electronic Testinges
dc.publication.volumen27es
dc.publication.issue3es
dc.publication.initialPage277es
dc.publication.endPage288es
dc.identifier.sisius6409113es
dc.contributor.funderGobierno de España
dc.contributor.funderJunta de Andalucía

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