Listar Ponencias (Instituto de Microelectrónica de Sevilla (IMSE-CNM)) por autor "Domínguez Castro, Rafael"
Mostrando ítems 1-20 de 43
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Ponencia
A 0.5 /spl mu/m CMOS CNN analog random access memory chip for massive image processing
(Institute of Electrical and Electronics Engineers, 1998)An analog RAM has been designed to act as a cache memory for a CNN Universal Machine. Hence, all the non-standard chips ...
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Ponencia
A countinuous-time cellular neural network chip for direction-selectable connected component detection with optical image acquisition
(Institute of Electrical and Electronics Engineers, 1994)This paper presents a continuous-time Cellular Neural Network (CNN) chip [1] for the application of Connected Component ...
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Ponencia
A mismatch-insensitive high-accuracy high-speed continuous-time current comparator in low voltage CMOS
(Institute of Electrical and Electronics Engineers, 1997)This paper presents a CMOS current comparator which employs nonlinear feedback to obtain high-accuracy (down to 1.5 pA) ...
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Ponencia
A mixed-signal early vision chip with embedded image and programming memories and digital I/O
(The International Society for Optical Engineering - SPIE, 2003)From a system level perspective, this paper presents a 128 × 128 flexible and reconfigurable Focal-Plane Analog Programmable ...
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Ponencia
A Model for VLSI implementation of CNN image processing chips using current-mode techniques
(Institute of Electrical and Electronics Engineers, 1993)A new Cellular Neural Network model is proposed which allows simpler and faster VLSI implementation than previous models. ...
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Ponencia
A multimode gray-scale CMOS optical sensor for visual computers
(Institute of Electrical and Electronics Engineers, 2002)This paper presents a new multimode optical sensor architecture for the optical interface of Visual CNN (cellular neural ...
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Ponencia
A one-transistor-synapse strategy for electrically-programmable massively-parallel analog array processors
(Institute of Electrical and Electronics Engineers, 1997)This paper presents a linear, four-quadrants, electrically-programmable, one-transistor synapse strategy applicable to the ...
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Ponencia
A processing element architecture for high-density focal plane analog programmable array processors
(Institute of Electrical and Electronics Engineers, 2002)The architecture of the elementary Processing Element - PE- used in a recently designed 128×128 Focal Plane Analog ...
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Ponencia
A prototype tool for optimum analog sizing using simulated annealing
(Institute of Electrical and Electronics Engineers, 1992)It is shown that using simulated annealing in combination with electrical simulation provides a powerful tool allowing ...
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Ponencia
A versatile sensor interface for programmable vision systems-on-chip
(The International Society for Optical Engineering - SPIE, 2003)This paper describes an optical sensor interface designed for a programmable mixed-signal vision chip. This chip has been ...
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Ponencia
Accurate design of analog CNN in CMOS digital technologies
(Institute of Electrical and Electronics Engineers, 1990)Explores the design of cellular neural networks (CNN) by using sampled-data analog current-mode techniques which neither ...
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Ponencia
ACE16K: A 128×128 focal plane analog processor with digital I/O
(Institute of Electrical and Electronics Engineers, 2002)This paper presents a new generation 128×128 focal-plane analog programmable array processor (FPAPAP), from a system level ...
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Ponencia
ACE16k: A programmable focal plane vision processor with 128 x 128 resolution
(European Conference on Circuit Theory and Design, 2001)This paper presents a new generation 128x128 Focal Plane Analog Programmable Array Processor (FPAPAP), from a system ...
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Ponencia
Analog integrated neural-like circuits for nonlinear programming
(Institute of Electrical and Electronics Engineers, 1989)A systematic approach for the design of analog neural nonlinear programming solvers using switched-capacitor (SC) integrated ...
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Ponencia
Analog neural networks for real-time constrained optimization
(Institute of Electrical and Electronics Engineers, 1990)Architectures and circuit techniques for implementing general piecewise constrained optimization problems using VLSI ...
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Ponencia
Analog weight buffering strategy for CNN chips
(Institute of Electrical and Electronics Engineers, 2003)Large, gray-scale CNN chips employ analog signals to achieve high-density in the internal distribution of the template ...
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Ponencia
Architectures and building blocks for CMOS VLSI analog "neural" programmable optimizers
(Institute of Electrical and Electronics Engineers, 1992)A modular reconfigurable serial architecture is presented for the analog/digital implementation of constrained optimization ...
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Ponencia
Bio-inspired analog parallel array processor chip with programmable spatio-temporal dynamics
(Institute of Electrical and Electronics Engineers, 2002)A bio-inspired model for an analog parallel array processor (APAP), based on studies on the vertebrate retina, permits the ...
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Ponencia
Challenges in mixed-signal IC design of CNN chips in submicron CMOS
(Institute of Electrical and Electronics Engineers, 1998)Summary form only given. The contrast observed between the performance of artificial vision machines and "natural" vision ...
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Ponencia
CMOS Architectures and circuits for high-speed decision-making from image flows
(The International Society for Optical Engineering (SPIE), 2008)We present architectures, CMOS circuits and CMOS chips to process image flows at very high speed. This is achieved by ...