Ponencia
Performance Evaluation of RAM-Based Implementation of Finite State Machines in FPGAs
Autor/es | Senhadji Navarro, Raouf
García Vargas, Ignacio Guisado Lizar, José Luis |
Departamento | Universidad de Sevilla. Departamento de Arquitectura y Tecnología de Computadores |
Fecha de publicación | 2012 |
Fecha de depósito | 2018-05-08 |
Publicado en |
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ISBN/ISSN | 978-1-4673-1261-5 |
Resumen | This paper presents a study of performance of
RAM-based implementations in FPGAs of Finite State Machines
(FSMs). The influence of the FSM characteristics on speed and
area has been studied, taking into account the ... This paper presents a study of performance of RAM-based implementations in FPGAs of Finite State Machines (FSMs). The influence of the FSM characteristics on speed and area has been studied, taking into account the particular features of different FPGA families, like the size of LUTs, the size of memory blocks, the number of embedded multiplexer levels and the specific decoding logic for distributed RAM. Our study can be useful for efficiently implementing FPGA-based state machines. |
Cita | Senhadji Navarro, R., García Vargas, I. y Guisado Lízar, J.L. (2012). Performance Evaluation of RAM-Based Implementation of Finite State Machines in FPGAs. En ICECS 2012: 19th IEEE International Conference on Electronics, Circuits, and Systems (225-228), Sevilla, España: IEEE Computer Society. |
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