Presentation
High-order cascade multi-bit Σ∆ modulators for high-speed A/D conversion
Author/s | Río Fernández, Rocío del
![]() ![]() ![]() ![]() ![]() ![]() ![]() Medeiro Hidalgo, Fernando Pérez Verdú, Belén Rodríguez Vázquez, Ángel Benito ![]() ![]() ![]() ![]() ![]() ![]() ![]() |
Department | Universidad de Sevilla. Departamento de Electrónica y Electromagnetismo |
Publication Date | 1998 |
Deposit Date | 2016-01-22 |
Published in |
|
ISBN/ISSN | 8460683457 |
Abstract | The use of Sigma-Delta (Σ∆) modulation
for analog-to-digital conversion (ADC) in the
communication frequency range is evaluated. Two
high-order multi-bit architectures are proposed to
achieve +12-bit dynamic range at ... The use of Sigma-Delta (Σ∆) modulation for analog-to-digital conversion (ADC) in the communication frequency range is evaluated. Two high-order multi-bit architectures are proposed to achieve +12-bit dynamic range at 4Msample/s Nyquist rate using very low oversampling ratio. They show very low sensitivity to the internal D-to-A conversion (DAC) error with no calibration required. Simulations show that such performance can be achieved even in presence of circuit imperfections |
Files | Size | Format | View | Description |
---|---|---|---|---|
Higher_order_cascade.pdf | 4.300Mb | ![]() | View/ | |