Article
Statistical threshold voltage shifts caused by BTI and HCI at nominal and accelerated conditions
Author/s | Díaz Fortuny, Javier
Saraza Canflanca, Pablo Rodríguez, Rosana Martín Martínez, Javier Castro López, Rafael Roca, Elisenda Fernández Fernández, Francisco Vidal Nafria, Montserrat |
Department | Universidad de Sevilla. Departamento de Electrónica y Electromagnetismo |
Publication Date | 2021-11 |
Deposit Date | 2024-09-10 |
Published in |
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Abstract | In nowadays deeply scaled CMOS technologies, time-zero and time-dependent variability effects have become important concerns for analog and digital circuit design. For instance, transistor parameter shifts caused by Bias ... In nowadays deeply scaled CMOS technologies, time-zero and time-dependent variability effects have become important concerns for analog and digital circuit design. For instance, transistor parameter shifts caused by Bias Temperature Instability and Hot-Carrier Injection phenomena can lead to progressive deviations of the circuit performance or even to its catastrophic failure. In this scenario, and to understand the effects of these variability sources, an extensive and accurate device characterization under several test conditions has become an unavoidable step towards trustworthy implementing the stochastic reliability models and simulation tools needed to achieve reliable integrated circuits. In this paper, the statistical distributions of threshold voltage shifts in nanometric CMOS transistors will be studied at nominal and accelerated aging conditions. To this end, a versatile transistor array chip and a flexible measurement setup have been used to reduce the required testing time to attainable values. |
Funding agencies | Agencia Estatal de Investigación. España |
Project ID. | TEC2016-75151-C3-R
PID2019-103869RB |
Citation | Díaz Fortuny, J., Saraza Canflanca, P., Rodríguez, R., Martín Martínez, J., Castro López, R., Roca, E.,...,Nafria, M. (2021). Statistical threshold voltage shifts caused by BTI and HCI at nominal and accelerated conditions. Solid-State Electronics, 185, 108037. https://doi.org/10.1016/j.sse.2021.108037. |
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