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Ponencia
Determinación del coeficiente de resolución en biestables RS CMOS
(Universidad Politécnica de Madrid. Laboratorio de Sistemas Integrados, 1992)
El diseño de biestables con riesgo de metaestabilidad requiere que posean coeficientes de resolución adecuados. En este trabajo, se introducen dos métodos para su medida y se comparan con otro previamente reportado. Uno ...
Ponencia
Delay degradation effect in submicronic CMOS inverters
(Université Catholique de Louvain, 1997)
This communication presents the evidence of a degradation effect causing important reductions in the delay of a CMOS inverter when consecutive input transition are close in time. Complete understanding of the effect is ...
Ponencia
Inertial and Degradation Delay Model for CMOS Logic Gates
(IEEE Computer Society, 2000)
The authors present the Inertial and Degradation Delay Model (IDDM) for CMOS digital simulation. The model combines the Degradation Delay Model presented in previous papers with a new algorithm to handle the inertial ...
Ponencia
Asymmetric clock driver for improved power and noise performances
(IEEE Computer Society, 2007)
One of the most important sources of switching noise and power consumption in large VLSI circuits is the clock generation and distribution tree. This paper analyzes how the use of an asymmetric clock can be an ...
Ponencia
Gate-Level Simulation of CMOS Circuits Using the IDDM Model
(IEEE Computer Society, 2001)
Timing verification of digital CMOS circuits is a key point in the design process. In this contribution we present the extension to gates of the Inertial and Degradation Delay Model for logic timing simulation which is ...
Ponencia
Aplicación del VHDL en prácticas de diseño de sistemas digitales
(Universidad Politécnica de Madrid, 1994)
Ponencia
Modeling of Real Bistables in VHDL
(IEEE Computer Society, 1993)
A complete VHDL model of bistables including their metastable operation is presented. An RS-NAND latch has been modelled as a basic structure, orienting its implementation towards its inclusion in a cell library. Two ...
Ponencia
HALOTIS: high accuracy LOgic TIming simulator with inertial and degradation delay model
(IEEE Computer Society, 2001)
This communication presents HALOTIS, a novel high accuracy logic timing simulation tool, that incorporates a new simulation algorithm based on different concepts for transitions and events. This new simulation algorithm ...
Ponencia
Hamming-code based fault detection design methodology for block ciphers
(IEEE Computer Society, 2020)
Fault injection, in particular Differential Fault Analysis (DFA), has become one of the main methods for exploiting vulnerabilities into the block ciphers currently used in a multitude of applications. In order to ...
Ponencia
Arquitectura para el diseño de circuitos autotemporizados bidimensionales. Realización de multiplicadores
(Universidad de Málaga, 1993)
La realización de sistemas digitales mediante técnicas autotemporizadas constituye la mejor alternativa para resolver la problemática de las técnicas síncronas en circuitos VLSI. En esta comunicación se presenta una mejora ...