Buscar
Mostrando ítems 291-300 de 301
Ponencia
Performance Comparison of Time-Step-Driven versus Event-Driven Neural State Update Approaches in SpiNNaker
(IEEE. Institute of Electrical and Electronics Engineers, 2018)
The SpiNNaker chip is a multi-core processor optimized for neuromorphic applications. Many SpiNNaker chips are assembled to make a highly parallel million core platform. This system can be used for simulation of a large ...
Ponencia
Image convolution using a probabilistic mapper on USB-AER board
(IEEE Computer Society, 2008)
In this demo we propose a method for computing real time convolution on AER images. For that we use signed events. The AER events produced on an AER retina or an image/video to AER conversor, are processed using ...
Ponencia
Real time multiple objects tracking based on a bioinspired processing cascade architecture
(IEEE Computer Society, 2010)
This paper presents a cascade architecture for bio-inspired information processing. We use AER (Address Event Representation) for transmitting and processing visual information provided by an asynchronous temporal contrast ...
Ponencia
Multi-Hop Synchronization at the Application Layer of Wireless and Satellite Networks
(IEEE Computer Society, 2008)
Time synchronization is a key issue in wireless and satellite networks; time-stamping collected data, tasks scheduling or efficient communications are just some applications. From all the existing techniques to achieve ...
Ponencia
Tools for Address-Event-Representation Communication Systems and Debugging
(Springer, 2005)
Address-Event-Representation (AER) is a communications protocol for transferring spikes between bio-inspired chips. Such systems may consist of a hierarchical structure with several chips that transmit spikes among them ...
Ponencia
Design of adaptive nano/CMOS neural architectures
(IEEE Computer Society, 2012)
Memristive devices are a promising technology to implement dense learning synapse arrays emulating the high memory capacity and connectivity of biological brains. Recently, the implementation of STDP learning in memristive ...
Ponencia
Performance Analysis of a Parallel Discrete Model for the Simulation of Laser Dynamics
(IEEE Computer Society, 2006)
This paper presents an analysis on the performance of a parallel implementation of a discrete model of laser dynamics, which is based on cellular automata. The performance of a 2D parallel version of the model is studied ...
Ponencia
Ponencia
Performance Evaluation of RAM-Based Implementation of Finite State Machines in FPGAs
(IEEE Computer Society, 2012)
This paper presents a study of performance of RAM-based implementations in FPGAs of Finite State Machines (FSMs). The influence of the FSM characteristics on speed and area has been studied, taking into account the ...
Ponencia
Determination of a Power-Saving Method for Real- Time Wireless Sensor Networks
(IEEE Computer Society, 2010)
In wireless sensor networks, battery life is a key resource that must be conserved as much as possible. Nowadays, the main way of achieve power saving in this type of circuits is to implement low-power RF (Radio Frequency) ...