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Mostrando ítems 1-10 de 16
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On scalable spiking convnet hardware for cortex-like visual sensory processing systems
(IEEE Computer Society, 2010)
This paper summarizes how Convolutional Neural Networks (ConvNets) can be implemented in hardware using Spiking neural network Address-Event-Representation (AER) technology, for sophisticated pattern and object recognition ...
Ponencia
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LVDS interface for AER links with burst mode operation capability
(IEEE Computer Society, 2008)
This paper presents the design and simulation of a serial AER LVDS communication link. It converts data from classical AER parallel bus with a 4-phase handshaking protocol into a bit stream which is transmitted serially ...
Ponencia
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High-Speed Character Recognition System based on a complex hierarchical AER architecture
(IEEE Computer Society, 2008)
In this paper we briefly summarize the fundamental properties of spikes processing applied to artificial vision systems. This sensing and processing technology is capable of very high speed throughput, because it does ...
Ponencia
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OTA-C oscillator with low frequency variations for on-chip clock generation in serial LVDS-AER links
(IEEE Computer Society, 2009)
This paper presents the design and simulation of an OTA-C oscillator intended to be used as on-chip frequency reference. This reference will be part of the high speed clock generation circuit for Manchester serial LVDS-AER ...
Ponencia
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Neocortical frame-free vision sensing and processing through scalable Spiking ConvNet hardware
(IEEE Computer Society, 2010)
This paper summarizes how Convolutional Neural Networks (ConvNets) can be implemented in hardware using Spiking neural network Address-Event-Representation (AER) technology, for sophisticated pattern and object recognition ...
Ponencia
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Voltage Mode Driver for Low Power Transmission of High Speed Serial AER Links
(IEEE Computer Society, 2011)
This paper presents a voltage-mode high speed driver to transmit serial AER data in scalable multi-chip AER systems. To take advantage of the asynchronous nature of AER (Address Event Representation) streams, this ...
Ponencia
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ConvNets Experiments on SpiNNaker
(IEEE Computer Society, 2015)
The SpiNNaker Hardware platform allows emulating generic neural network topologies, where each neuronto- neuron connection is defined by an independent synaptic weight. Consequently, weight storage requires an ...
Ponencia
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Event based vision sensing and processing
(IEEE Computer Society, 2008)
In this paper we briefly summarize the fundamental properties of spike events processing applied to artificial vision systems. This sensing and processing technology is capable of very high speed throughput, because it ...
Ponencia
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Event-Driven Configurable Module with Refractory Mechanism for ConvNets on FPGA
(IEEE Computer Society, 2018)
We have developed a fully configurable event-driven convolutional module with refractory period mechanism that can be used to implement arbitrary Convolutional Neural Networks (ConvNets) on FPGAs following a 2D array ...
Ponencia
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Fully Digital AER Convolution Chip for Vision Processing
(IEEE Computer Society, 2008)
We present a neuromorphic fully digital convolution microchip for Address Event Representation (AER) spike-based processing systems. This microchip computes 2-D convolutions with a programmable kernel in real time. It ...