Listar Ponencias (Instituto de Microelectrónica de Sevilla (IMSE-CNM)) por título
Mostrando ítems 107-126 de 307
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Ponencia
Cell-culture Real-Time Monitoring: an Oscillation-based Approach
(Universidad de Sevilla, 2013)In this work, a way to cell-culture real-time monitoring system by means of the Oscillation-Based Test (OBT) methodology ...
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Ponencia
Challenges in mixed-signal IC design of CNN chips in submicron CMOS
(Institute of Electrical and Electronics Engineers, 1998)Summary form only given. The contrast observed between the performance of artificial vision machines and "natural" vision ...
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Ponencia
Characterization of electrical crosstalk in 4T-APS arrays using TCAD simulations
(Institute of Electrical and Electronics Engineers, 2017)TCAD simulations have been conducted on a CMOS image sensor in order to characterize the electrical component of the ...
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Ponencia
CMOS analog neural network systems based on oscillatory neurons
(Institute of Electrical and Electronics Engineers, 1992)This paper addresses the design of two neural network systems based on the use of pulsing neurons. Each neuron is built ...
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Ponencia
CMOS Architectures and circuits for high-speed decision-making from image flows
(The International Society for Optical Engineering (SPIE), 2008)We present architectures, CMOS circuits and CMOS chips to process image flows at very high speed. This is achieved by ...
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Ponencia
CMOS circuit implementations for neuron models
(Institute of Electrical and Electronics Engineers, 1990)The mathematical neuron basic cells used as basic cells in popular neural network architectures and algorithms are discussed. ...
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Ponencia
CMOS current-mode chaotic neurons
(Institute of Electrical and Electronics Engineers, 1994)This paper presents two nonlinear CMOS current-mode circuits that implement neuron soma equations for chaotic neural ...
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Ponencia
CMOS design of adaptive fuzzy ASICs using mixed-signal circuits
(Institute of Electrical and Electronics Engineers, 1996)Analog circuits are natural candidates to design fuzzy chips with optimum speed/power figures for precision up to about ...
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Ponencia
CMOS design of cellular APAPs and FPAPAPs: an overview
(Institute of Electrical and Electronics Engineers, 2002)CNN-based analog visual microprocessors have similarities with the so-called Single Instruction Multiple Data systems, ...
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Ponencia
CMOS design of chaotic oscillators using state variables: a monolithic Chua's circuit
(Institute of Electrical and Electronics Engineers, 1993)This paper presents design considerations for monolithic implementation of piecewise-linear (PWL) dynamic systems in CMOS ...
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Ponencia
CMOS mixed-signal MODEM for data transmission and control of electrical household appliances using the low-voltage power-line
(The International Society for Optical Engineering - SPIE, 2003)This paper presents a CMOS 0.6μm mixed-signal MODEM ASIC for data transmission using the low-voltage power line. This ...
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Ponencia
CMOS realization of a 2-layer CNN universal machine chip
(Institute of Electrical and Electronics Engineers, 2002)Some of the features of the biological retina can be modelled by a cellular neural network (CNN) composed of two dynamically ...
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Ponencia
CMOS SPADs selection, modeling and characterization towards image sensors implementation
(Institute of Electrical and Electronics Engineers, 2012)The selection, modeling and characterization of Single Photon Avalanche Diodes (SPADs) are presented. Working with the ...
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Ponencia
CNN technology in action
(Institute of Electrical and Electronics Engineers, 2000)Two Cellular Neural Net Universal Machine (CNN-UM) prototypes are demonstrated in action. The first one is the latest 4096 ...
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Ponencia
CNN universal chip in CMOS technology
(Institute of Electrical and Electronics Engineers, 1994)This paper describes the design of a CNN universal chip in a standard CMOS technology. The core of the chip consists of ...
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Ponencia
Comparison of matroid intersection algorithms for large circuit analysis
(Institute of Electrical and Electronics Engineers, 1997)This paper presents two approaches to symbolic analysis of large analog integrated circuits via simplification during the ...
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Ponencia
Complementary tunnel gate topology to reduce crosstalk effects
(Institute of Electrical and Electronics Engineers (IEEE), 2017)Tunnel transistors are one of the most attractive steep subthreshold slope devices which are being investigated to overcome ...
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Ponencia
Compressive image sensor architecture with on-chip measurement matrix generation
(Institute of Electrical and Electronics Engineers, 2017)A CMOS image sensor architecture that uses a cellular automaton for the pseudo-random compressive sampling matrix generation ...
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Ponencia
Continuous-time cascaded ΣΔ modulators for VDSL: A comparative study
(The International Society for Optical Engineering - SPIE, 2005)This paper describes new cascaded continuous-time ΣΔ modulators intended to cope with very high-rate digital subscriber ...
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Ponencia
Control and acquisition system for a high dynamic range CMOS image sensor
(Institute of Electrical and Electronics Engineers, 2012)A control and acquisition system for the visualization of the images captured with a High Dynamic Range (HDR) CMOS Image ...