Listar Ponencias (Instituto de Microelectrónica de Sevilla (IMSE-CNM)) por título
Mostrando ítems 87-106 de 307
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Ponencia
An error-controlled methodology for approximate hierarchical symbolic analysis
(Institute of Electrical and Electronics Engineers, 2000)Limitations of existing approaches for symbolic analysis of large analog circuits are discussed. To address their solution, ...
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Ponencia
An Experimentally-Validated Verilog-A SPAD Model Extracted from TCAD Simulation
(Institute of Electrical and Electronics Engineers, 2018)Single-photon avalanche diodes (SPAD) are photodetectors with exceptional characteristics. This paper proposes a new ...
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Ponencia
An Optimization-based Tool for the High-Level Synthesis of Discrete-time and continuous-Time Sigma-Delta Modulators in the MATLAB/SIMULINK Environment
(Institute of Electrical and Electronics Engineers, 2004)This paper presents a MATLAB toolbox for the automated high-level sizing of ΣΔ Modulators (ΣΔMs) based on the combination ...
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Ponencia
An ultra-low-power voltage-mode asynchronous WTA-LTA circuit
(Institute of Electrical and Electronics Engineers, 2013)This paper presents an asynchronous mixed-signal WTA-LTA circuit conceived to carry out local minimummaximum indexing ...
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Ponencia
Analog integrated neural-like circuits for nonlinear programming
(Institute of Electrical and Electronics Engineers, 1989)A systematic approach for the design of analog neural nonlinear programming solvers using switched-capacitor (SC) integrated ...
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Ponencia
Analog neural networks for real-time constrained optimization
(Institute of Electrical and Electronics Engineers, 1990)Architectures and circuit techniques for implementing general piecewise constrained optimization problems using VLSI ...
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Ponencia
Analog weight buffering strategy for CNN chips
(Institute of Electrical and Electronics Engineers, 2003)Large, gray-scale CNN chips employ analog signals to achieve high-density in the internal distribution of the template ...
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Ponencia
Analysis and Experimental Characterization of Idle Tones in 2nd-Order Bandpass Sigma-Delta Modulators - A 0.8μm CMOS Switched-Current Case Study
(Institute of Electrical and Electronics Engineers, 2001)Ths paper analyses the tonal behaviour of the quantization noise in 2nd-order bandpass SD modulators. The analysis previously ...
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Ponencia
Analysis and Modeling of the Non-Linear Sampling Process in Switched-Current Circuits - Application to Bandpass Sigma-Delta Modulators
(2001)This paper presents a precise model for the transient behaviour of Fully Differential (FD) SwItched-current (SI) memory ...
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Ponencia
Analysis of Clock Jitter Error in Multibit Continuous-Time ΣΔ modulators with NRZ Feedback Waveform
(Institute of Electrical and Electronics Engineers, 2005)This paper presents a detailed study of the clock jitter error in multibit continuous-time ΣΔ modulators with non-return-to-zero ...
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Ponencia
Application of piecewise-linear switched-capacitor circuits for random number generation
(Institute of Electrical and Electronics Engineers, 1989)An unconventional application of switched-capacitor (SC) circuits is discussed. A systematic method for the design of ...
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Ponencia
Architectures and building blocks for CMOS VLSI analog "neural" programmable optimizers
(Institute of Electrical and Electronics Engineers, 1992)A modular reconfigurable serial architecture is presented for the analog/digital implementation of constrained optimization ...
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Ponencia
Artifact-Aware Analogue/Mixed-Signal Front-Ends for Neural Recording Applications
(Institute of Electrical and Electronics Engineers, 2019)This paper presents a brief review of techniques to overcome the problems associated with artifacts in analog frontends ...
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Ponencia
Assessing application areas for tunnel transistor technologies
(Institute of Electrical and Electronics Engineers (IEEE), 2016)Tunnel transistors are one of the most attractive steep subthreshold slope devices currently being investigated as a means ...
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Ponencia
Baseband-processor for a passive UHF RFID transponder
(Institute of Electrical and Electronics Engineers, 2010)This paper describes the design of a digital processor targeting the Class-1 Generation-2 EPC Protocol for UHF RFID ...
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Ponencia
Behavioral modeling of PWL analog circuits using symbolic analysis
(Institute of Electrical and Electronics Engineers, 1998)Behavioral models are used both for top-down design and for bottom-up verification. During top-down design, models are ...
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Ponencia
Behavioral Modeling, Simulation and High-Level Synthesis of Pipeline A/D Converters
(2005)This paper presents a MATLAB® toolbox for the time-domain simulation and high-level sizing of pipeline analog-to-digital ...
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Ponencia
Bio-inspired 0.35μm CMOS Time-to-Digital Converter with 29.3ps LSB
(Institute of Electrical and Electronics Engineers, 2006)Time-to-digital converter (TDC) integrated circuit is introduced in this paper. It is based on chain of delay elements ...
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Ponencia
Bio-inspired analog parallel array processor chip with programmable spatio-temporal dynamics
(Institute of Electrical and Electronics Engineers, 2002)A bio-inspired model for an analog parallel array processor (APAP), based on studies on the vertebrate retina, permits the ...
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Ponencia
Boundary cost optimization for Alternate Test
(Institute of Electrical and Electronics Engineers, 2015)Alternate Test has demonstrated in the last decade that advanced machine-learning tools can leverage the accuracy gap ...