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Now showing items 11-20 of 117
Presentation
Modular Design of Adaptive Analog CMOS Fuzzy Controller Chips
(Institute of Electrical and Electronics Engineers, 1995)
Analog circuits are natural candidates to design fuzzy chips with optimum speed/power figures for precision up to about 1%. This paper presents a methodology and circuit blocks to realize fuzzy controllers in the form of ...
Presentation
CMOS design of chaotic oscillators using state variables: a monolithic Chua's circuit
(Institute of Electrical and Electronics Engineers, 1993)
This paper presents design considerations for monolithic implementation of piecewise-linear (PWL) dynamic systems in CMOS technology. Starting from a review of available CMOS circuit primitives and their respective merits ...
Article
Design considerations for integrated continuous-time chaotic oscillators
(Institute of Electrical and Electronics Engineers, 1998)
This paper presents an optimization procedure to choose the chaotic state equation which is best suited for implementation using Gm-C integrated circuit techniques. The paper also presents an analysis of the most significant ...
Presentation
Modeling OpAmp-induced harmonic distortion for switched-capacitor ΣΔ modulator design
(Institute of Electrical and Electronics Engineers, 1994)
This communication reports a new modeling of opamp-induced harmonic distortion in SC ΣΔ modulators, which is aimed to optimum design of this kind of circuit for high-performance applications. We analyze incomplete transfer ...
Article
Switched-Current Chaotic Neurons
(Institution of Engineering and Technology, 1994)
The Letter presents two nonlinear CMOS current-mode circuits that implement neuron soma equations for chaotic neural networks. They have been fabricated in a double-metal, single-poly 1.6µm CMOS technology. The neuron soma ...
Presentation
Architectures and building blocks for CMOS VLSI analog "neural" programmable optimizers
(Institute of Electrical and Electronics Engineers, 1992)
A modular reconfigurable serial architecture is presented for the analog/digital implementation of constrained optimization algorithms with digital programmability of the problem weights. Area overhead due to programmability ...
Article
A 0.8-μm CMOS two-dimensional programmable mixed-signal focal-plane array processor with on-chip binary imaging and instructions storage
(Institute of Electrical and Electronics Engineers, 1997)
This paper presents a CMOS chip for the parallel acquisition and concurrent analog processing of two-dimensional (2-D) binary images. Its processing function is determined by a reduced set of 19 analog coefficients whose ...
Presentation
A countinuous-time cellular neural network chip for direction-selectable connected component detection with optical image acquisition
(Institute of Electrical and Electronics Engineers, 1994)
This paper presents a continuous-time Cellular Neural Network (CNN) chip [1] for the application of Connected Component Detection (CCDet) [2]. Projection direction can be selected among four different possibilities. Every ...
Presentation
A Tool for automated design of sigma-delta modulators using statistical optimization
(Institute of Electrical and Electronics Engineers, 1993)
A tool is presented which starting from high level specifications of SC σδ modulators (resolution, bandwidth and oversampling ratio) calculates first optimum specifications for the building blocks (op-amps, comparator, ...
Presentation
A multiplexed mixed-signal fuzzy architecture
(Institute of Electrical and Electronics Engineers, 1998)
Analog circuits provide better area/power efficiency than their digital counterparts for low-medium precision requirements. This limit in precision as well as the lack of design tools when compared to the digital approach, ...