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Mostrando ítems 21-30 de 117
Ponencia
Hysteresis based neural oscillators for VLSI implementations
(Institute of Electrical and Electronics Engineers, 1991)
The actual tendency in most of the work that is being done in VLSI neural network research is to use the simplest possible models to perform the desired tasks. This yields to the use of sigmoidal type neurons that have ...
Ponencia
Mixed-signal CNN array chips for image processing
(The International Society for Optical Engineering, 1996)
Due to their local connectivity and wide functional capabilities, cellular nonlinear networks (CNN) are excellent candidates for the implementation of image processing algorithms using VLSI analog parallel arrays. However, ...
Ponencia
Discrete-time integrated circuits for chaotic communication
(Institute of Electrical and Electronics Engineers, 1997)
This paper gives design considerations for the synthesis of analog discrete-time encoder-decoder pairs based on digital filter structures with overflow non-linearity. Simulation results from an integrated prototype using ...
Artículo
Analog Neural Programmable Optimizers in CMOS VLSI Technologies
(Institute of Electrical and Electronics Engineers, 1992)
A 3-μm CMOS IC is presented demonstrating the concept of an analog neural system for constrained optimization. A serial time-multiplexed general-purpose architecture is introduced for the real-time solution of this kind ...
Ponencia
An algorithm for numerical reference generation in symbolic analysis of large analog circuits
(Institute of Electrical and Electronics Engineers, 1997)
This paper addresses the problems arising in the calculation of numerical references (network function coefficients), essential for an appropriate error control in simplification before and during generation algorithms for ...
Ponencia
A fourth-order bandpass ΣΔ modulator using current-mode analog/digital circuits
(Institute of Electrical and Electronics Engineers, 1996)
We present a fourth-order bandpass ΣΔ switched-current modulator IC in 0.8 μm CMOS single-poly technology. Its architecture is obtained by applying a lowpass to bandpass transformation (z-1 →-z-2) to a second-order lowpass ...
Artículo
SIRENA: A CAD environment for behavioural modelling and simulation of VLSI cellular neural network chips
(Wiley-Blackwell, 1999)
This paper presents SIRENA, a CAD environment for the simulation and modelling of mixed-signal VLSI parallel processing chips based on cellular neural networks. SIRENA includes capabilities for: (a) the description of ...
Ponencia
CMOS analog neural network systems based on oscillatory neurons
(Institute of Electrical and Electronics Engineers, 1992)
This paper addresses the design of two neural network systems based on the use of pulsing neurons. Each neuron is built as a simple voltage controlled oscillator (VCO) whose control voltage makes the circuit to oscillate ...
Ponencia
Ponencia
An accurate error control mechanism for simplification before generation algorithms
(Institute of Electrical and Electronics Engineers, 1999)
The use of simplification before generation techniques to enable the approximate symbolic analysis of large analog circuits is discussed. This paper introduces an error control mechanism to drive the circuit reduction, ...