Presentation
A Methodology for MOS Transistor Mismatch Parameter Extraction and Mismatch Simulation
Author/s | Serrano Gotarredona, María Teresa
Linares Barranco, Bernabé |
Department | Universidad de Sevilla. Departamento de Arquitectura y Tecnología de Computadores |
Publication Date | 2000 |
Deposit Date | 2020-09-30 |
Published in |
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ISBN/ISSN | 0-7803-5482-6 |
Abstract | This paper presents a methodology for mismatch parameter extraction and mismatch simulation using conventional electrical simulators, like HSpice. A measurement and extraction procedure has been carefully designed to be ... This paper presents a methodology for mismatch parameter extraction and mismatch simulation using conventional electrical simulators, like HSpice. A measurement and extraction procedure has been carefully designed to be able to obtain reliable measurements of the mismatch parameters of a given technology. The correctness of this extraction procedure method has been checked through three different validation methods. We also present two methods for performing mismatch simulation with conventional circuit simulators (like HSpice) using the extracted parameters. |
Citation | Serrano Gotarredona, M.T. y Linares Barranco, B. (2000). A Methodology for MOS Transistor Mismatch Parameter Extraction and Mismatch Simulation. En ISCAS 2000: IEEE International Symposium on Circuits and Systems (109-112), Geneva, Switzerland: IEEE Computer Society. |
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