Ponencia
Analog weight buffering strategy for CNN chips
Autor/es | Liñán Cembrano, Gustavo
Rodríguez Vázquez, Ángel Benito Carmona Galán, Ricardo Espejo Meana, Servando Carlos Domínguez Castro, Rafael |
Departamento | Universidad de Sevilla. Departamento de Electrónica y Electromagnetismo |
Fecha de publicación | 2003 |
Fecha de depósito | 2019-10-31 |
Publicado en |
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ISBN/ISSN | 0-7803-7761-3 |
Resumen | Large, gray-scale CNN chips employ analog signals to achieve high-density in the internal distribution of the template parameters. Despite the design strategies adopted at the circuitry employed to implement the weights, ... Large, gray-scale CNN chips employ analog signals to achieve high-density in the internal distribution of the template parameters. Despite the design strategies adopted at the circuitry employed to implement the weights, accuracy is ultimately limited by the controlling signals. This paper presents a buffering strategy intended to achieve 8-bit equivalent accuracy in the distribution of the internal analog signals, as employed in the chips ACE4k, ACE16k, and CACE1k. |
Identificador del proyecto | TIC1999-0826 |
Cita | Liñán Cembrano, G., Rodríguez Vázquez, Á.B., Carmona Galán, R., Espejo Meana, S.C. y Domínguez Castro, R. (2003). Analog weight buffering strategy for CNN chips. En IEEE International Symposium on Circuits and Systems (ISCAS) (III-522-III-525), Bangkok, Tailandia: Institute of Electrical and Electronics Engineers. |
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