Ponencia
Discrete-time integrated circuits for chaotic communication
Autor/es | Delgado Restituto, Manuel
Rodríguez Vázquez, Ángel Benito |
Departamento | Universidad de Sevilla. Departamento de Electrónica y Electromagnetismo |
Fecha de publicación | 1997 |
Fecha de depósito | 2019-10-25 |
Publicado en |
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ISBN/ISSN | 0-7803-3583-X |
Resumen | This paper gives design considerations for the synthesis of analog discrete-time encoder-decoder pairs based on digital filter structures with overflow non-linearity. Simulation results from an integrated prototype using ... This paper gives design considerations for the synthesis of analog discrete-time encoder-decoder pairs based on digital filter structures with overflow non-linearity. Simulation results from an integrated prototype using switched-capacitor techniques and designed in a 0.8 /spl mu/m CMOS technology are presented to validate the suitability of these systems for information encryption. |
Cita | Delgado Restituto, M. y Rodríguez Vázquez, Á.B. (1997). Discrete-time integrated circuits for chaotic communication. En IEEE International Symposium on Circuits and Systems (ISCAS) (1073-7076), Hong Kong: Institute of Electrical and Electronics Engineers. |
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