dc.creator | Rodríguez Vázquez, Ángel Benito | es |
dc.creator | Carmona Galán, Ricardo | es |
dc.creator | Domínguez Matas, Carlos | es |
dc.creator | Suárez Cambre, Manuel | es |
dc.creator | Brea Sánchez, Víctor Manuel | es |
dc.creator | Pozas, Francisco | es |
dc.creator | Liñán Cembrano, Gustavo | es |
dc.creator | Foldessy, Peter | es |
dc.creator | Zarandy, Akos | es |
dc.creator | Rekeczky, Csaba | es |
dc.date.accessioned | 2019-08-12T10:12:08Z | |
dc.date.available | 2019-08-12T10:12:08Z | |
dc.date.issued | 2010 | |
dc.identifier.citation | Rodríguez Vázquez, Á.B., Carmona Galán, R., Domínguez Matas, C., Suárez Cambre, M., Brea Sánchez, V.M., Pozas, F.,...,Rekeczky, C. (2010). A 3-D Chip Architecture for Optical Sensing and Concurrent Processing. Proceedings of SPIE, 7726, 772613. | |
dc.identifier.issn | 1996-756X | es |
dc.identifier.uri | https://hdl.handle.net/11441/88350 | |
dc.description | Event: SPIE Photonics Europe, 2010, Brussels, Belgium | |
dc.description.abstract | This paper presents an architecture for the implementation of vision chips in 3-D integration technologies. This architecture
employs the multi-functional pixel concept to achieve full parallel processing of the information and hence high
processing speed. The top layer includes an array of optical sensors which are parallel-connected to the second layer,
consisting of an array of mixed-signal read-out and pre-processing cells. Multiplexing is employed so that each mixedsignal
cell handles several optical sensors. The two remaining layer are respectively a memory (used to store different
multi-scale images obtained at the mixed-signal layer) and an array of digital processors. A prototype of this architecture
has been implemented in a FDSOI CMOS-3D technology with Through-Silicon-Vias of 5μm x 5μm pitch. | es |
dc.description.sponsorship | Junta de Andalucía 2006-TIC-2352 | es |
dc.format | application/pdf | es |
dc.language.iso | eng | es |
dc.publisher | SPIE | es |
dc.relation.ispartof | Proceedings of SPIE, 7726, 772613. | |
dc.rights | Attribution-NonCommercial-NoDerivatives 4.0 Internacional | * |
dc.rights.uri | http://creativecommons.org/licenses/by-nc-nd/4.0/ | * |
dc.subject | 3-D Optical Sensors | es |
dc.subject | Vision Systems | es |
dc.subject | Navigation Applications | es |
dc.title | A 3-D Chip Architecture for Optical Sensing and Concurrent Processing | es |
dc.type | info:eu-repo/semantics/article | es |
dcterms.identifier | https://ror.org/03yxnpp24 | |
dc.type.version | info:eu-repo/semantics/publishedVersion | es |
dc.rights.accessRights | info:eu-repo/semantics/openAccess | es |
dc.contributor.affiliation | Universidad de Sevilla. Departamento de Electrónica y Electromagnetismo | es |
dc.relation.projectID | 2006-TIC-2352. | es |
dc.relation.publisherversion | https://doi.org/10.1117/12.855027 | es |
dc.identifier.doi | 10.1117/12.855027 | es |
idus.format.extent | 13 p. | es |
dc.journaltitle | Proceedings of SPIE | es |
dc.publication.volumen | 7726 | es |
dc.publication.initialPage | 772613 | es |