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A 14-bit 4-MS/s Multi-bit Cascade Sigma-Delta Modulator in CMOS 0.35-um Digital Technology

 

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Opened Access A 14-bit 4-MS/s Multi-bit Cascade Sigma-Delta Modulator in CMOS 0.35-um Digital Technology
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Author: Río Fernández, Rocío del
Medeiro Hidalgo, Fernando
Rosa Utrera, José Manuel de la
Pérez Verdú, Belén
Rodríguez Vázquez, Ángel Benito
Department: Universidad de Sevilla. Departamento de Electrónica y Electromagnetismo
Date: 2000
Document type: Presentation
Abstract: This paper presents a 4th-order 3-stage cascade SD modulator that achieves 14-bit dynamic range at 4MS/s using low oversampling ratio. It includes a programmable multi-bit quantizer in the last stage, providing 2-, 3-, or 4-bit internal resolution. The modulator is implemented with fully-differential switched capacitor circuits in a CMOS 0.35-mm digital technology. The estimated power consumption is 78mW, from a 3.3-V supply.
Size: 160.5Kb
Format: PDF

URI: https://hdl.handle.net/11441/80083

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Attribution-NonCommercial-NoDerivatives 4.0 Internacional

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