Ponencia
A 14-bit 4-MS/s Multi-bit Cascade Sigma-Delta Modulator in CMOS 0.35-um Digital Technology
Autor/es | Río Fernández, Rocío del
Medeiro Hidalgo, Fernando Rosa Utrera, José Manuel de la Pérez Verdú, Belén Rodríguez Vázquez, Ángel Benito |
Departamento | Universidad de Sevilla. Departamento de Electrónica y Electromagnetismo |
Fecha de publicación | 2000 |
Fecha de depósito | 2018-11-13 |
Publicado en |
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Resumen | This paper presents a 4th-order 3-stage cascade SD
modulator that achieves 14-bit dynamic range at
4MS/s using low oversampling ratio. It includes a programmable
multi-bit quantizer in the last stage, providing
2-, 3-, ... This paper presents a 4th-order 3-stage cascade SD modulator that achieves 14-bit dynamic range at 4MS/s using low oversampling ratio. It includes a programmable multi-bit quantizer in the last stage, providing 2-, 3-, or 4-bit internal resolution. The modulator is implemented with fully-differential switched capacitor circuits in a CMOS 0.35-mm digital technology. The estimated power consumption is 78mW, from a 3.3-V supply. |
Agencias financiadoras | European Union (UE) Comisión Interministerial de Ciencia y Tecnología (CICYT). España |
Identificador del proyecto | ESPRIT 29261
TIC 97-0580 |
Cita | Río Fernández, R.d., Medeiro Hidalgo, F., Rosa Utrera, J.M.d.l., Pérez Verdú, B. y Rodríguez Vázquez, Á.B. (2000). A 14-bit 4-MS/s Multi-bit Cascade Sigma-Delta Modulator in CMOS 0.35-um Digital Technology. En XV Design of Circuits and Integrated Systems Conference, Montpellier (Francia). |
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A 14-bit 4.pdf | 160.5Kb | [PDF] | Ver/ | |