Ponencia
Reliable analysis of settling errors in SC integrators - application to high-speed low-power ΣΔ modulators design
Autor/es | Río Fernández, Rocío del
Rosa Utrera, José Manuel de la Pérez Verdú, Belén Medeiro Hidalgo, Fernando Rodríguez Vázquez, Ángel Benito |
Departamento | Universidad de Sevilla. Departamento de Electrónica y Electromagnetismo |
Fecha de publicación | 1999 |
Fecha de depósito | 2018-10-22 |
Publicado en |
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Resumen | This paper presents a detailed study on the transient
response of SC integrators taking into account
the effects of amplifier finite gain-bandwidth product
and slew-rate during, unlike previous models, both
the integration ... This paper presents a detailed study on the transient response of SC integrators taking into account the effects of amplifier finite gain-bandwidth product and slew-rate during, unlike previous models, both the integration and sampling phases. Results are applied to the design of high-speed low-power SD modulators and simplified equations are obtained for manual-estimation of the settling error power. |
Agencias financiadoras | European Union (UE) Comisión Interministerial de Ciencia y Tecnología (CICYT). España |
Identificador del proyecto | ESPRIT 29261
TIC 97-0580 |
Cita | Río Fernández, R.d., Rosa Utrera, J.M.d.l., Pérez Verdú, B., Medeiro Hidalgo, F. y Rodríguez Vázquez, Á.B. (1999). Reliable analysis of settling errors in SC integrators - application to high-speed low-power ΣΔ modulators design. En XIV Design of Circuits and Integrated Systems Conference, Palma de Mallorca (España). |
Ficheros | Tamaño | Formato | Ver | Descripción |
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Reliable Analysis.pdf | 102.1Kb | [PDF] | Ver/ | |