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Reliable analysis of settling errors in SC integrators - application to high-speed low-power ΣΔ modulators design

 

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Opened Access Reliable analysis of settling errors in SC integrators - application to high-speed low-power ΣΔ modulators design
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Author: Río Fernández, Rocío del
Rosa Utrera, José Manuel de la
Pérez Verdú, Belén
Medeiro Hidalgo, Fernando
Rodríguez Vázquez, Ángel Benito
Department: Universidad de Sevilla. Departamento de Electrónica y Electromagnetismo
Date: 1999
Published in: XIV Design of Circuits and Integrated Systems Conference (1999), p 1-6
Document type: Presentation
Abstract: This paper presents a detailed study on the transient response of SC integrators taking into account the effects of amplifier finite gain-bandwidth product and slew-rate during, unlike previous models, both the integration and sampling phases. Results are applied to the design of high-speed low-power SD modulators and simplified equations are obtained for manual-estimation of the settling error power.
Cite: Río Fernández, R.d., Rosa Utrera, J.M.d.l., Pérez Verdú, B., Medeiro Hidalgo, F. y Rodríguez Vázquez, Á.B. (1999). Reliable analysis of settling errors in SC integrators - application to high-speed low-power ΣΔ modulators design. En XIV Design of Circuits and Integrated Systems Conference, Palma de Mallorca (España).
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URI: https://hdl.handle.net/11441/79577

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