Ponencia
Offset-compensated comparator with full-input range in 150nm FDSOI CMOS-3d technology
Autor/es | Suárez Cambre, Manuel
Brea Sánchez, Víctor Manuel Domínguez Matas, Carlos Carmona Galán, Ricardo Liñán Cembrano, Gustavo Rodríguez Vázquez, Ángel Benito |
Departamento | Universidad de Sevilla. Departamento de Electrónica y Electromagnetismo |
Fecha de publicación | 2010 |
Fecha de depósito | 2018-07-31 |
Publicado en |
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ISBN/ISSN | 978-1-5090-2076-8 |
Resumen | This paper addresses an offset-compensated comparator
with full-input range in the 150nm FDSOI CMOS-
3D technology from MIT- Lincoln Laboratory. The comparator
discussed here makes part of a vision system. Its architecture ... This paper addresses an offset-compensated comparator with full-input range in the 150nm FDSOI CMOS- 3D technology from MIT- Lincoln Laboratory. The comparator discussed here makes part of a vision system. Its architecture is that of a self-biased inverter with dynamic offset correction. At simulation level, the comparator can reach a resolution of 0.1mV in an area of approximately 220μm2 with a time response of less than 40ns and a static power dissipation of 1.125μW. |
Cita | Suárez Cambre, M., Brea Sánchez, V.M., Domínguez Matas, C., Carmona Galán, R., Liñán Cembrano, G. y Rodríguez Vázquez, Á.B. (2010). Offset-compensated comparator with full-input range in 150nm FDSOI CMOS-3d technology. En Latin American Symposium on Circuits ans Systems (1-4), Iguazu (Brasil): Institute of Electrical and Electronics Engineers. |
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